Method and apparatus for rectification derectification and power flow control

ABSTRACT

A method of transferring energy from a power source into an output node including the steps of separately charging each of a plurality of energy storage elements from the power source; after the plurality of energy storage elements are charged, discharging a selected one of the energy storage elements through an inductive element into the output node; and as the selected energy storage element is being discharged through the inductive element, when its voltage reaches a preselected value, discharging another one of the energy storage elements through the inductive element into the output node.

BACKGROUND OF THE INVENTION

The invention relates to AC to DC power conversion, rectification,derectification, and power flow control.

Standard rectification using diode brides causes both harmonics and areactive power on the AC line. This is because power is drawn from theline when its AC voltage is higher than the output voltage and no poweris drawn from the line when its AC voltage is lower than the outputvoltage. This uneven loading of the line throughout the AC cycleintroduces harmonics onto the line. Current is only drawn out of thesystem when the voltage is high relative to the output voltage. As aconsequence, conventional bridge or half wave rectification techniquesseriously distort the input waveform. This problem is solved by usingharmonic filters and capacitors to eliminate the harmonics. In addition,filtering is added on the DC side to reduce ripple that the processestends to cause.

In an earlier patent (i.e., U.S. Pat. No. 5,270,913 filed Apr. 6, 1992,and incorporated herein by reference), I described a transformerlesspower conversion system (referred to hereinafter as PCS). In verygeneral terms, the PCS works by charging a set of capacitors from apower source, possibly transforming the voltage across the set ofcapacitors by inverting the voltages on selected capacitors, and thendischarging the set of capacitors at the transformed voltage into adistribution node or load. In other words, a complete cycle of operationin the PCS includes a charging phase, possibly an inversion phase, and adischarging phase. By employing many cycles of operation per second(e.g. 1 to 2 kHz), the PCS can extract charge from the power source andinject it into the distribution node or load to reconstruct an outputhaving a desired waveform. The PCS is extremely versatile in thetransformations which it can be configured to perform. For example, itcan be configured to convert AC to DC, DC to DC with step-up orstep-down, DC to AC, or AC of one frequency to AC of another frequency,to name a few.

In the case of AC to DC conversion, charging the PCS from a low voltagesource (e.g. when the instantaneous voltage of the input AC waveform islow) presents the same type of problem that is encountered withconventional rectification. If the transformed voltage in the PCS isless than at least two times the output voltage, it will not be possibleto fully discharge the capacitors into the DC output terminal.Therefore, it follows that the PCS system can also impose a nonuniformload on the input line and thereby distort the input waveform byintroducing harmonics back onto the input line.

As described in the earlier patent, however, this problem can be solvedby using multiple charging cycles per discharge cycle. In this way, theoutput voltage of the PCS can be made sufficiently high to permit acomplete discharge of the storage capacitors during the discharge cycle.Though that technique works, it may be more complex than necessary, itinvolves more computation, and it requires capacitors with highervoltage ratings.

SUMMARY OF THE INVENTION

In general, in one aspect, the invention is a system for controlling VARof a multiphase grid. The system includes a plurality of charge storageelements; a plurality of charge transfer circuits each connected to acorresponding phase of the multiphase grid and to a corresponding one ofthe plurality of charge storage elements; and a charge redistributioncircuit connected to the plurality of charge storage elements, whereinduring operation the charge redistribution circuit redistributes chargeamong the plurality of charge storage devices.

In preferred embodiments, the system further includes a controller whichoperates the plurality of charge transfer circuits and the chargeredistribution circuit, wherein during operation the controller causesthe plurality of charge transfer circuits to transfer charge to theplurality of charge storage elements, causes the charge redistributioncircuit to redistribute the charge that was transferred to the pluralitycharge storage elements, and causes the charge transfer circuit totransfer the redistributed charge to the grid.

In general, in yet still another aspect, the invention is a power flowcontrol system for connecting to a multiphase grid. The system includesa plurality of charge storage elements; a plurality of charge transfercircuits each connected to a corresponding phase of the multiphase gridand to a corresponding one of the plurality of charge storage elements;a charge redistribution circuit connected to the plurality of chargestorage elements, wherein during operation the charge redistributioncircuit redistributes charge among the plurality of charge storagedevices; and a controller operates the plurality of charge transfercircuits and the charge redistribution circuit, wherein said controllercontrols the power flow into the system by establishing non-zero initialconditions on the plurality of charge storage elements prior to a chargetransfer cycle during which charge is exchanged between the grid and thecharge storage elements.

In general, in another aspect, the invention is a derectification systemfor generating from a power source a multiphase AC output onto a grid.The system includes a plurality of charge storage elements; a firstcharge transfer circuit which charges the plurality of charge storageelements from the power source; a second charge transfer circuit whichtransfers charge between the plurality of storage elements and themultiphase grid; and a controller which operates the first and secondcharge transfer circuits, wherein the controller causes the secondtransfer circuit to discharge the plurality of charge storage elementsonto the grid in order of increasing voltage, starting with the chargestorage element with the lowest voltage and ending with the chargestorage element with the highest voltage.

In general, in a further aspect, the invention is a method of operatinga system including a plurality of charge storage elements that arecoupled to a power source through a circuit which includes an inductor.The method is for generating a multiphase AC output onto a grid andincludes the steps of sequentially transferring charge between the powersource and each of the plurality of charge storage elements so that eachof the charge storage elements is characterized by a voltagecorresponding to the charge stored therein; and transferring chargebetween each of the plurality of charge storage elements and acorresponding one of the phases on the grid, wherein the step ofsequentially transferring charge is performed in order of increasingvoltage on the charge storage elements.

In general, in still another aspect, the invention a method ofcontrolling power flow between a multiphase grid and a system whichincludes a plurality of charge storage elements. The method includesestablishing non-zero initial conditions on the plurality of chargestorage elements, and then transferring charge between the multiphasegrid and the plurality of charge storage elements.

One very attractive application of the sequential discharge technique isfor a harmonic-free conversion of multi-phase AC power to DC and in ACto AC waveform reconstruction. By charging a capacitor, the sequentialdischarge technique allows the energy extraction from any phase of amulti-phase AC line to be proportional to the square of the momentaryline voltage. Performing the charging at constant intervals loads the ACline to the desired power level at any part of the AC cycle. Thisenables one to load the multi-phase AC line uniformly and maintain abalanced and constant power. Since the load which the rectificationtechnique imposes on the multiple phase inputs is equivalent to aresistive load, it produces no harmonic distortions that must befiltered out. Thus, the sequential discharge technique substantiallyeliminates the generation of harmonics. Though the rectificationapproach of the invention includes about the same number of componentsas a conventional bridge rectification approach, it completelyeliminates the need for expensive, harmonic filters on the input side ofthe system. Thus, the invention permits the elimination of harmonicfilters, VAR capacitor banks, and DC ripple filters. In addition, theload current is in phase with the AC voltage, yielding a unity powerfactor. This eliminates the requirement for phase angle correction.

The invention is particularly well suited for application to multiphaseAC input but it may be also may be used for other specializedoperations. For example, the same technique can also be used in a moreeffective AC to AC asynchronous power conversion system and otherapplications.

The invention may also be used in conjunction with a PCS yieldingtransformation and rectification for either voltage step-up orstep-down. The invention significantly simplifies control and operationof the PCS system and permits a larger power throughput. When used inconnection with the PCS, the PCS does not store any significant amountof energy in the conversion process. Therefore, as a consequence of theconstant power throughput, the DC output is ripple-free, which alsosaves on filtering on the DC side. Full and continued regulation isobtained for both applications. This rectification system is relativelysimple and could be used for many industrial applications.

An attractive application of the invention would be to rectify andstep-up the power from an AC source and feed it directly into a two-line(plus and minus) DC overland transmission line. For existing converters,it is necessary to install filters to reduce harmonics on the AC sideand a ripple filter on the DC side. Such filters are of considerablesize and form an appreciable part of the power generation costs. Theproblem comes from the fact that standard rectification techniques loadthe AC lines disproportionately at the higher voltage part of the ACcycle.

The potential uses of the invention in the industrial world aremanifold. Efficient and harmonic-free rectification is required for manyapplications. For the purposes of DC transmission, AC rectification hasto be performed on a large scale and high voltage level. Approximately12% of US power is consumed for the production of aluminum. In addition,industry uses electrowinning and electrolytic refining processing forthe production of sodium, magnesium, copper, silver, lead, nickel, zinc,chlorine, fluorine and hydrogen. And this is not a complete list.

The rectification of AC power is also required for most motor drives,where AC is rectified to DC and then the DC is converted back to AChaving the desired frequency. An additional application is inUninterruptible Power Supplies (UPS) where the AC input is typicallyrectified and converted back to AC. Using the invention, energy can beextracted from the grid without distorting the voltage on the grid.Moreover, the extracted energy can then be used to generate a new ACwaveform at the desired frequency using the transformation techniquesthat were described in U.S. Pat. No. 5,270,913 or using other standardDC conversion techniques. This technique is also very useful forvariable speed motor control.

In addition, a rectification steps are required in many other areas. Forexample, rectification is used in the front end of UPS (uninterruptiblePower Supplies) and other temporary battery power storage. Moreover,once the electric car gets on the road, these vehicles will need to becharged during the night from an AC grid. To that, add the potential ofinductive energy storage, where electric energy is stored in largemagnetic coils to be used during peak consumption or short powerinterruption.

There has been a significant increase in nonlinear loads that are beingattached to the grid. This increase has prompted an increased concernabout harmonics. Harmonic current flow in the power system as reactivepower (VAR), adds to the increased apparent power demand of nonlinearloads. The harmonic current causes additional heat and stress on thepower system components due to their higher frequency. For somecomponents, such as transformers, the derating for harmonic currents canbe substantial (e.g. 30% to 40%).

Industry standards are being formulated to limit harmonics in the powersystem and to encourage the development of electrical loads that do notgenerate harmonics. Two such standards are IEC 555 and IEEE 519. IEC 555limits the levels of harmonic current generated from individual loadequipment connected to public power systems in Europe. In the US, IEEE519 has been revived to establish recommended limits on the level ofharmonics that users can inject into the public power system. The use ofthe three phase rectification system which embodies the invention wouldeliminate harmonics generation in the rectification system.

Other advantages and features will become apparent from the followingdescription of the preferred embodiment and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit which is used to illustrate the sequential dischargetechnique;

FIG. 2 is a plot of the various operating regions of the circuit of FIG.1;

FIG. 3A shows plots of the output current, I_(out), of the circuit ofFIG. 1 as a function of time for different values of V₀₂ (for firstoperating mode);

FIG. 3B shows plots of the capacitor voltages, V₁ and V₂, as a functionof time for different values of V₀₂ (for first operating mode);

FIG. 4A shows plots of the output current, I_(out), of the circuit ofFIG. 1 as a function of time for different values of V₀₂ (for secondoperating mode);

FIG. 4B shows plots of the capacitor voltages, V₁ and V₂, as a functionof time for different values of V₀₂ (for second operating mode);

FIG. 5 is a circuit diagram of a sequential discharging circuit for usewith a three phase line;

FIGS. 6A and B present a plot of the input and output current andvoltage waveforms for the circuit shown in FIG. 1;

FIG. 7 is a circuit diagram of another charging and sequentialdischarging circuit for use with a three phase line;

FIG. 8 is a circuit diagram of a sequential discharging circuit for usewith a six phase power source;

FIG. 9 is an example of a center-tapped transformer for use ingenerating two phases from a single phase line;

FIG. 10A shows a simple zero crossing detector circuit;

FIG. 10B shows the voltage waveforms on the primary and the secondary ofthe transformer used in the zero crossing detector circuit of FIG. 10A;

FIG. 11 is a circuit diagram of a circuit which uses sequentialdischarge in connection with a step-down pulse transformer;

FIG. 12 is a modified version of the circuit shown in FIG. 11 includingtwo sets of input capacitors for increased throughput;

FIG. 13 is another modified sequential discharge rectification circuitwhich employs a phase-to-phase input section;

FIG. 14 is a circuit diagram of a PCS with a transformer coupled inputsection;

FIG. 15 is an equivalent circuit of the transformer shown in FIG. 14;

FIG. 16 is a circuit diagram of a PCS with a dual polarity transformercoupled input section;

FIG. 17 is a circuit diagram of a PCS with a transformer coupled outputsection;

FIG. 18 is a simple charging circuit;

FIG. 19 is an example of an AC to AC frequency changer circuit whichembodies the invention;

FIG. 20 is a derectification circuit;

FIG. 21a is a plot of interpulse duration for the triggering of theSCR's in a derectification circuit which uses an input common bridgecricuit;

FIG. 21b is a plot of β for the triggering of the SCR's in aderectification circuit which uses an input common bridge circuit;

FIG. 22a is a plot of the current through the resonant charging inductorduring an illustrative charging cycle of the derectification circuit;

FIG. 22b is a plot of the voltage at the output of the charging inductorduring a charging cycle of the derectification circuit;

FIG. 23 is a plot of power throughput versus frequency of an AC to ACfrequency changer;

FIG. 24(a) is a standard voltage source inverter;

FIG. 24(b) is a standard current source inverter;

FIG. 25 is a schematic of a simplified Static VAR Generator with activeharmonic filter capability;

FIG. 26 shows a plot of the voltages in the static VAR circuit of FIG.25 during one cycle of operation for the case that all capacitors areindividually discharged before redistribution of charge takes place;

FIG. 27 shows another plot of the voltages in the static VAR circuit ofFIG. 25 during one cycle of operation and for the case that twocapacitors are discharged/charged simultaneously during each step;

FIG. 28 is a schematic of an active harmonic filter circuit;

FIG. 29 is a schematic of a simplified AC to AC frequency changercircuit;

FIG. 30 is a block diagram of power flow control system;

FIG. 31 is a plot of real and reactive power flow;

FIG. 32 is a plot of total power flow for one phase showing a periodduring which negative power flow occurs;

FIG. 33 is a schematic of a redistribution network; and

FIG. 34 is a plot of the voltage across Cm1 in the derectificationcircuit of FIG. 20.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Overview of the Sequential Discharge Technique:

To illustrate the invention and to make some representative numericalcomputations, we will use the sequential discharge circuit 10 shown inFIG. 1. Circuit 10 includes two capacitors, C₁ and C₂, from which powerwill be extracted into a load 20 to produce an output voltage, V_(out).It should be understood that there is an implied charging system infront of the capacitors. For example, the capacitors might be thecapacitors of a PCS module that is configured to provide DC step-up orstep-down module, such as is described in U.S. Pat. No. 5,270,913. Orthe capacitors might be the output capacitors of a simple LC chargingstage, an example of which will be presented later (see FIG. 7). Ingeneral, the capacitors are first charged during a charging cycle tosome predetermined level and then they are sequentially discharged intoload 20 during a discharge cycle.

Circuit 10 includes two discharge paths 22 and 24, one connected tocapacitor C₁ and the other connected to capacitor C₂. The firstdischarge path includes a silicon controlled rectifier, SCR₁, that isconnected through inductor L to load 20. The second discharge pathincludes a second silicon controlled rectifier, SCR₂, that is alsoconnected through the same inductor L to load 20. SCR₁ and SCR₂ arearranged so that when they are triggered on they discharge theirrespective capacitors through inductor L. A free wheeling diode 26 isconnected between ground and the side of inductor L to which SCR₁ andSCR₂ are connected. Free wheeling diode prevents the voltage on eitherof the capacitors to reversing at the end of a complete discharge. Aprogrammable control unit 23 (e.g. a computer or general data processingunit) samples the voltages across the capacitors V₁ and V₂, samples theoutput voltage V_(out), and triggers the SCR's at the appropriate times.

In general, discharge circuit 10 discharges capacitors C₁ and C₂ insequence and through the shared output inductor L. In addition, forevery charge cycle, there is a discharge cycle in which both capacitorsare typically discharged. The capacitor with the highest voltage isdischarged first, followed by the discharge of the capacitor with thelower voltage. If properly timed, the excess energy from the highvoltage input module helps to pull out the energy from the low voltageinput module. This method enables input charging to occur at constantintervals and thus it reduces the computational requirements.

As an aside, it should be understood that the term "load" when usedherein, is meant to have a very general meaning unless indicatedotherwise by the specification or the context in which it is being used.It includes a node, a power distribution point, a motor, a simpleresistive load, the input of a circuit to which power is being supplied,etc. In addition, though we have referred to SCR's in this andsubsequent embodiments, any of a wide variety of switching devices canbe substituted for the SCR, depending upon the requirements of theparticular application, including, for example, thyristors, Crossatrons,GTO's, any semiconductor unidirectional switching devices, etc.

The following discussion presents the details of a discharging cyclethat immediately follows a charging cycle during which capacitors C₁ andC₂ are charged to initial voltages of V₀₁ and V₀₂, respectively. For thefollowing discussion, we assume the output voltage to be V_(out) =10 kVand an initial voltage condition of V₀₁ >V₀₂.

Two different sequential discharge modes of operation will be described.In both modes of operation, it is assumed that the voltage V₀₁ isgreater than or equal to twice the output voltage V_(out) and SCR₁ istriggered first to discharge C₁ and then SCR₂ is triggered to dischargeC₂. The requirement that V₀₁ ≧V_(out) is necessary in order to assurethat C₁ will completely discharge during its discharge cycle. In thefollowing example, we select V₀₁ =25 kV which meets this requirement.The difference between the two modes is in the timing of the triggeringof SCR₂. In the first mode, SCR₂ is triggered when V₁ reaches zerovolts. In the second mode, SCR₂ is triggered when V₁ reaches the valueof V₀₂.

When SCR₁ is triggered, capacitor C₁ discharges through inductor L intooutput load 20. At the end of discharge (i.e., when V₁ equal zero), freewheeling diode 26 prevents the voltage on C₁ from reversing and itpermits the energy remaining in the inductor L to be transferred tooutput load 20. At the point that V₁ reaches zero, the current in theinductor is given by: ##EQU1## and at that point the energy stored inthe inductor L is: ##EQU2##

If we trigger SCR₂ when V₁ reaches 0 and connect capacitor C₂ throughinductor L to output load 20, the current in the inductor, I_(out),represents an initial condition for the discharge of the secondcapacitor C₂. Thus, there will be a certain range of voltages V₂ <2V_(out) for which it will be possible to fully discharge the capacitorC₂. If V₀₂ ≧2 V_(out), then sequential discharge is not required, sincethe voltage on C₂ is sufficiently large to enable the capacitor tocompletely discharge by itself. However, sequential discharging maystill be used in this case in order to combine the effect of the excessvoltage of C₁ and C₂ to aid in discharging additional capacitors thathave lower voltage levels.

The range of voltages less than 2 V_(out) for which this is true can besolved either analytically, graphically, or with the use of circuitmodeling codes. If we plot the voltage and current for a discharge witha capacitor r volt age equal to twice that of the output voltage, boththe voltage and current will be zero at the end of the discharge. If welook at the curve, we will find that for any current th at is less thanthe maximum current of: ##EQU3## the capacitor voltage V₂ has twosolutions. The two solutions correspond to the initial voltages thatcapacitor C₂ must have in order to fully discharge all of the energyfrom capacitor C₂. If the initial voltage of C₂ is between those twosolutions, the capacitor cannot be completely discharged. If currentremains in inductor L when V₂ reaches zero, an additional capacitor,such as the input from a third phase, can then be discharged.

As should be readily apparent, the energy and voltage in each capacitorvaries throughout the 60 Hz cycle if the capacitors are charged from theAC grid. However, what may not be so apparent is that the total energyof all of the capacitors is constant and that this is true for anynumber of capacitors charged from a multi-phase power source with anynumber of phases larger than one. This fact has a very importantimplication. It does not matter when in the 60 Hz cycle the discharge isbegun since the total energy in all of the capacitors remains constantthroughout the cycle. Thus, there will be a constant power flow throughthe circuit so long as the capacitors are completely discharged and theyare originally charged at constant time intervals.

The complete discharge of C₁ and C₂ is possible only if their initialconditions are properly selected. V₀₁ must be at least 2 V_(out) toenable it to fully discharge into a node that is at V_(out). Even if V₀₁is above 2 V_(out), if it is not sufficiently above 2 V_(out), theresidual current that remains in inductor L when V₁ reaches zero may notbe sufficient to cause the complete discharge of C₂ into the node atV_(out). FIG. 2 presents a plot of the different operating regions ofthe circuit shown in FIG. 1. The x-axis represents the ratio of theinitial voltage across C₁ to the output voltage (i.e., V₀₁ /V_(out));and the y-axis represents the ratio of the initial voltage across C₂ tothe output voltage (i.e., V₀₂ /V_(out)).

If the initial voltages on capacitors C₁ and C₂ are properly selected,both capacitors can be fully discharged at the end of a sequentialdischarge cycle, with no residual current remaining in inductor L. Theset of conditions which produce such a result are shown by curve 30. Theequation for curve 30 is as follows:

    V.sub.02 =V.sub.out ±(V.sub.out.sup.2 -V.sub.01.sup.2 +2×V.sub.out ×V.sub.01).sup.1/2

The condition can be put in a simpler form:

    E.sub.1 +E.sub.2 =2×(E.sub.1.sup.1/2 +E.sub.2.sup.1/2)

where E_(m) is the ratio of the initial energy stored in capacitor C_(m)divided by the energy remaining when its voltage equals the outputvoltage, V_(out). If the condition is such that the left side of theequation is smaller than the right side, then the initial conditionfalls to the left of the curve in the FIG. 2 and the second capacitorcannot be discharged.

If the initial conditions fall within the region to the left of curve 30but to the right of V₀₁ /V_(out) =2.0, then it will be possible to fullydischarge capacitor C₁ but not capacitor C₂. In the region to the leftof the line V₀₁ /V_(out) =2.0, it will not be possible to fullydischarge either C₁ or C₂.

If initial conditions fall within the region to the right of curve 30,then both capacitors can be fully discharged through sequentialdischarging with some residual current remaining in inductor L. As notedabove, the residual current in inductor L can supply the initialcondition for discharging a third capacitor (not shown), where thecombined condition of the first two capacitors, if appropriatelyselected, will permit the full discharge of the third capacitor.Following the above reasoning, it should be apparent that the solutionfor V₀₃ (i.e., the voltage(s) at which full discharge is possible) willhave four roots or, once the voltage for the first two capacitors isspecified, two roots. This process can be continued as long as aresidual inductor current remains on subsequent discharges. Thedischarge sequence is best performed with the discharge of capacitors inthe order of decreasing voltages.

FIGS. 3A and 3B show simulated output current and voltage waveforms,respectively, for one complete discharge cycle of operation of theabove-described sequential discharge technique. In this example, SCR₁ istriggered first and when V₁ reaches zero volts, SCR₂ is triggered. Theinitial voltage V₀₁ was selected to be 25 kV and V₀₂ is some smallervalue, as indicated on the curves. By selecting V₀₁ to be 2.5 times theoutput voltage V_(out), this permits the full discharge of C₂ over thecomplete range of initial voltages that C₂ might have. If the voltageV₀₁ is between 25 kV and 20 kV, the voltage range for V₀₂ which willallow full discharge is restricted in the manner which will be describedbelow. For the numerical calculations that were performed, thecapacitors all had values of 1 μF and the inductors all had values of6.338 mH. In FIGS. 2A and 2B, the family of curves represent thedifferent values of V₀₂, i.e., the initial voltage across C₂.

As indicated in FIG. 3A, the output current I_(out) through inductor Lis relatively large at the time that V₁ reaches zero volts and SCR₂ istriggered on. This residual current helps to completely pull out thecharge that is stored in C₂. As indicated in FIG. 3B, the voltage acrossC₂ remains at V₀₂ until SCR₂ is triggered on and then C₂ fullydischarges to zero volts. It should be apparent that in all cases thereis a residual current remaining in L_(out) at the point that C₂ is fullydischarged. In this case, free wheeling diode 26 provides a bypass pathfor the residual current in inductor L allowing the inductor tocompletely discharge and preventing its residual current from reversingthe voltage on any of the capacitors. As noted earlier, the residualcurrent could instead be used to discharge yet another capacitor ifthere were more input stages in the circuit.

As noted earlier, sequential discharge may also be performed in a secondmode. Instead of triggering the second discharge at the point when thevoltage of C₁ is zero, one may trigger it at the point when V₁ reachesV₀₂, the initial voltage of the second capacitor. By triggering at thispoint, both capacitors are effectively connected in parallel and arebeing discharged together. The current and voltage waveform for thistype of discharge sequence are shown in FIGS. 4A and 4B, respectively.

Both sequential discharge modes of operation yield about the samedischarge periods and require similar components. The first approach(i.e., triggering SCR₂ when V₁ reaches zero) has the advantage thatcorrect timing of the second phase of discharging is easier toaccomplish. From an operational point of view, the second approach(i.e., triggering SCR₂ when V₁ reaches V₀₂) is more difficult toimplement. In the second mode of operation, if the timing of the startof the discharge of the second phase is not accurate, the firstcapacitor will not be fully discharged.

Sequential Discharge Rectification (SDR)

To summarize what was presented above, the sequential dischargerectification technique involves discharging in sequence all inputmodules (e.g. capacitors or PCS modules) through a shared outputinductor using a shared free-wheeling diode. In addition, the modulesare discharged in decreasing order of the initial module voltage. Theexcess energy remaining in the output inductor from the discharge of thefirst module helps "pull out" energy from the capacitors of the secondand third modules, which have lower voltage levels.

An output section for three phase rectification circuit is shown in FIG.5. One SCR per phase (i.e., (SCR₁ SCR₂, and SCR₃) discharges acorresponding capacitor (C_(ph1), C_(ph2), and C_(ph3)) into a sharedoutput inductor L_(out), which is, in turn, connected through a filtersection 27 to a load 30. Filter section 27 filters out any ripples thatare caused by the pulsed discharge of the capacitors into the load.

The components of a low-pass output filter are also shown in FIG. 5 inthe dashed box. Note that the illustrated filter design is very simple,consisting only of three reactive elements: L_(f), C_(f1) and C_(f2),connected as shown. Since the energy is dumped into C_(f1), itscapacitance should by at least about 3-5 times larger than thecapacitance of the storage capacitors, C_(phi). By selecting a filtercut-off point that is lower than the lowest expected repetition rate ofthe circuit, a smooth output voltage is produced. The filter can, ofcourse, be of any appropriate design which is capable of eliminating theripple that the sequential discharge tends to introduce.

As noted previously, the shared output inductor is a key component forthe sequential discharge operation since it allows any residual currentremaining from the discharge of one capacitor to assist in achieving thecomplete discharge of another capacitor.

Capacitors, C_(ph1), C_(ph2), and C_(ph3), each represent a differentcapacitor (in this case, "stack of capacitors") within a correspondingPCS module (not shown). Each PCS module is connected to a differentphase of a three phase AC line. In other words, each capacitor ischarged to a voltage that is proportional to the absolute voltage of thecorresponding AC input phase at that time. It is assumed for purposes ofthis example that the PCS modules each provide a step-up factor of N.Thus, the voltages across each of the capacitors can be determined asfollows: ##EQU4## where "A" is the AC input voltage amplitude and N isthe step up ratio of the PCS module.

As before, a programmed control unit 23 controls the operation of thecharging circuit and the sequential discharge circuit (e.g. thetriggering of the SCR's).

The capacitor voltages for the three phases are shown in Table I over anangle of 60 degrees (see columns labeled Phase 1, Phase 2, and Phase 3).The numbers are for an rms input voltage of 11 kV and a step-up ratio ofN=6. Table I has eight entries separated in time by 7.5 electricaldegrees.

                  TABLE I                                                         ______________________________________                                        Time     Phase 1 Phase 2    Phase 3                                                                             Triggering                                  (msec)   (Volt)  (Volt)     (Volt)                                                                              Sequence                                    ______________________________________                                        0.174     7,049  89,618      96,657                                                                             3-2-1                                       0.521    21,026  81,036     102,053                                                                             3-2-1                                       0.868    34,643  71,068     105,704                                                                             3-2-1                                       1.215    47,667  59,885     107,546                                                                             3-2-1                                       1.563    59,876  47,676     107,548                                                                             3-1-2                                       1.910    71,060  34,652     105,710                                                                             3-1-2                                       2.257    81,030  21,036     102,063                                                                             3-1-2                                       2.604    89,612   7,059      96,670                                                                             3-1-2                                       ______________________________________                                    

By triggering the charging cycle at the listed times the correspondingcapacitor voltages are obtained. Identical voltage combinations arerepeated every 60 degrees with the cyclic shift of all the columns tothe right.

The SCR's are triggered starting with the capacitor having the highestvoltage and proceeding sequentially through the rest of the capacitor inorder of decreasing voltage. For each charge cycle, the dischargesequence is as shown in the last column of Table I. For example, look atthe entries in the row at time 0.174 msec. The charging cycle associatedat that time establishes voltages on C_(ph1), C_(ph2), and C_(ph3) of7,049, 89,618, and 96,657 volts, respectively. Given the relativeordering of the capacitor voltages, the discharge will be in thefollowing order: C_(ph3), C_(ph2), and C_(ph1).

It can be simply shown, either mathematically or numerically, that thecombined energy of the three capacitors is at all times a constant andis given by: ##EQU5##

The quantity of combined charged energy is independent of the phaseangle and source frequency. In other words, the combined energy isidentical for each and every charge cycle. It follows that if one simplycharges and discharges these capacitors together at controlled timeintervals, the input power and output power can be independent in timeand no synchronization with the AC cycle is required.

Also, by charging each capacitor at constant time intervals, the energyextracted from each line is proportional to the square of theinstantaneous voltage. This is exactly what the power flow is into aresistive load. It therefore follows that by using this power extractionmethod, the power factor of the AC input is identical to unity and noreactive power flow occurs.

Control circuit 23 monitors the load and sets the repetition rate basedupon the required throughput that is demanded by the load. If the loador the input voltage changes, a simple feedback loop can adjust thefrequency at which the charging/discharging cycles occur to maintain aconstant output voltage.

FIGS. 6A and 6B show, respectively, the input voltage waveform 40 andthe input current waveform 42 over 60 degrees of a 60 Hz three-phaseinput, with the capacitors charged to the voltage levels listed in TableII. (Note that in this case "input" refers to the input of the outputfilter 27.) As can be seen, the input condition of the second 30 degreesis the image of the first 30 degrees. In addition, the input conditionis repeated every 60 degrees. FIG. 6A presents the capacitor voltage ofthe switched on capacitors and the inductor current. As can be seen fromthe current discontinuities, the inductor current is substantial by thetime the second and third capacitors are switched on line. In addition,the inductor and free-wheeling diode current do not have to be zerobetween consecutive capacitor discharge cycles.

In FIGS. 6A and 6B, the charging of the three capacitors occurs at thesame time. It is assumed that the charging time required to charge eachof the capacitors through a corresponding input inductor (not shown)takes about 250 μsec. This determines how frequently the capacitors canbe charged and how soon one discharge cycle can follow a previousdischarge cycle. It should be noted that to generate the waveforms thatare shown, in particular, the repetition frequency of the dischargecycle, there is implied (but not shown for purposes of simplifying thecircuit) a second set charging and discharging circuits, including threeadditional capacitors. The second set of circuits is coupled into thecircuit shown in FIG. 5 in parallel with the illustrated set ofdischarging circuits. Each of the capacitors in the othercharging/discharging circuits is coupled to shared inductor L_(out)through a corresponding SCR. While the first set of capacitors (i.e.,C_(ph1), C_(ph2), and C_(ph3)) is being discharged, the second set ofcapacitors (not shown) is being charged. In this way, there will alwaysbe a set of capacitors that is immediately available for the nextdischarge cycle without having to wait for a charging cycle to beperformed. Thus, the circuit can be operated at a higher repetitionrate.

FIGS. 6A and 6B also show the low pass output filter voltage 46 andoutput current 48. Of prime importance is that both the output currentand output voltage are constant. Not shown, but of equal importance, isthat both the input voltage and input current of all three phases issinusoidal and ripple-free even with the use of small low-pass inputfilters.

Note that as the repetition rate increases so does the ripple frequency.If the low-pass output filter section is designed to handle the lowestrepetition rate that is anticipated for the system, it will then handlethe higher ripple frequencies that are produced at faster repetitionrates.

If thyristors are used for the SCR's, they should have a rapid recoveryrate, i.e., a short t_(Q). Since the discharge is completed within about250 μsec, the SCR's will see forward bias in about 125 μsec. They needto be recovered before they experience the forward voltage. Thyristorshaving the required recovery are available commercially.

For the conditions described above, the output capacitor values are 9.1nF, the load is 7 kΩ for a total power throughput of 225 kW. A muchhigher throughput can be obtained by using a single string of standardand unparalleled high voltage thyristors for the SCR's. Using typical 8kA thyristors, an output power of over 200 MW can be obtained with oneset of three modules. The same technique can be used in the lower orconsumer voltage range. In this regime faster and lower voltageswitching devices can be used with a higher switching speed and lowerforward voltage drop. This will lead to a more optimized throughput andhigher efficiency.

Alternative SDR Configurations:

For rectification applications, the capacitor voltages must always bethe same polarity as the output voltage to transfer power out of thesystem into the load. Since the input voltage to the charging circuit isnegative over half of the input waveform cycle, this portion of thewaveform cannot be used. This problem can be solved in at least twoways. One approach is to allow the input capacitors to charge to anegative voltage and then use an inversion cycle to flip the voltage toa positive value. The inclusion of the inversion cycle in this laterapproach reduces the maximum repetition rate that is achievable with thesystem. Another approach is to generate six phases. Thus, there willalways be input waveforms having positive polarity throughout the entirecycle. Examples of these two approaches are described below.

An alternative three phase rectification circuit without transformation(i.e., without using the PCS module for transforming the input waveform)is shown in FIG. 7. The three phases of the AC input line arerepresented by the inputs labeled Phase 1, Phase 2, and Phase 3. Thecircuit includes three charging circuits 60(1-3), one for each phase,for charging a corresponding one of three capacitors, C₁, C₂, and C₃.The charging circuit for C₁ includes an input filter section 70(1), apair of SCR's (i.e., SCR_(in1+) and SCR_(in1-)) and an input inductor,L_(in1). SCR_(in1+) is for charging C₁ from the positive polarityportion of the AC input waveform and SCR_(in1-) is for charging C₁ fromthe negative polarity portion of the AC input waveform. The chargingcircuits for the other two capacitors (i.e., C₂ and C₃) are constructedidentically to the first charging circuit and thus their correspondingcomponents are similarly labeled.

Each capacitor is resonantly charged through its input inductor from theinput phase to which it is connected. For example, C₁ is resonantlycharged through L_(in1) from phase 1, and similarly for the othercapacitors. Thus, the charging period is determined by the selection ofthe value of the input inductor.

On a three phase line, at any given time there will be either one or twophases which have negative polarity. Thus, the correspondingcapacitor(s) will be resonantly charged to a negative voltage. Aninversion circuit connected across the capacitor invert the negativevoltage after the charging cycle is complete and prior to the dischargecycle. In the case of capacitor C₁, the inversion circuit includes aninductor L_(i1) and silicon controlled rectifier SCR_(i1). Similarinversion circuits are connected across the other capacitors C₂ and C₃.With the inverting circuits, all three capacitors can be made positiveprior to the discharge cycle even though they were charged from anegative portion of the input waveform. This simply requires theinclusion of an inverting cycle between the charging cycle and thedischarging cycle. Thus, all three phases can contribute to everydischarging cycle.

In this rectification circuit of FIG. 7, the discharge circuits areconstructed basically as previously described. Each capacitor C₁, C₂,and C₃, is connected through a corresponding one of SCR's (i.e.,SCR_(oi1), SCR_(oi2), and SCR_(oi3)) into a shared output inductorL_(out). The other side of L_(out) is connected through an output ripplefilter to a load 62 (e.g. power distribution node). A control unit (notshown) controls the triggering of the SCR's to produce the charging,inversion, and discharging cycles of operation.

If a six-phase source is available, the inversion components and theinversion cycle can be eliminated, as shown in FIG. 8. The circuit isthe same as that shown in FIG. 7 except that each capacitor can becharged from two phases of the six phase source. Thus, for example,capacitor C₁, which is resonantly charged through L_(in1), is connectedto Phase 1 through SCR_(in1), and to Phase 4 through SCR_(in4). The twophases from which C₁ is charged are selected to be 180° out of phasewith each other so that when the voltage of one waveform is negative thevoltage of the other waveform is positive. The charging of each of theother capacitors C₂ and C₃. Thus, at all times throughout the AC cycle,each capacitor can be charged from a positive voltage source. With thisarrangement, the inverting circuit are not needed; instead, thetriggering of the SCR's is controlled to correctly select that Phasefrom which power will be extract during each charging cycle.

The configuration of FIG. 8 provides each input phase with the correctpolarity, requires no inversion, and permits a 50% higher throughputthan for the three-phase throughput. This configuration can be furtherexploited by adding a second rectification circuit of identical designto generate both a positive and a negative DC output polarity.

For large power systems, the six phases can be generated simply by usingtwo sets of transformers with half of full ratio. A three phase systemcan be easily converted to a six phase system with the use ofcenter-tapped transformers, such as are shown in FIG. 9. The center tapof the secondary is the neutral line and the outside lines of thesecondary furnish the two phases, one being the inverse of the other.

The six-phase rectification and step-up may also be attractive withtransformation. The complexity of the transformation modules can bereduced depending on power throughput. In addition, efficiency can beincreased and triggering requirements reduced, since several diodes canbe used in place of SCRs.

Another beneficial configuration is rectification of a six-phase powersource generating a plus and minus DC output source. The six phases maybe made available with small modifications of generators by bringing outthree additional phases from the generator windings. Using the typicaloutput of 10 kV a one-step rectification and step-up to a voltage rangeof ±40 to ±120 kV can be obtained with a power level in excess of 100MW.

Control Module:

The interpulse separation sets the output voltage to the desired level.The algorithm for controlling the interpulse separation or repetitionrate of the charging/discharging cycles is straight forward. Note thatthe same amount of energy is taken in per pulse of operation. Thus, thepower throughput of the system is proportional to A² ×(repetition rate).If the input voltage drops by 10%, the power throughput will drop byabout 20%. To compensate for the 10% drop in input voltage, therepetition rate must be increased by about 20%. Similarly, if the outputpower drops by 10% (e.g. because loading is less), then to compensate,the repetition rate must be decreased by 10%. If the repetition rate isnot decreased, the output voltage will rise.

By measuring the input voltage, the output voltage, and the outputcurrent, one has all of the information that is required to control theoperation of the system.

To accurately set the firing sequence, it is necessary to know where youare within the cycle of the input waveform. This can easily bedetermined by locating the zero crossings of the waveform. One approachto detecting the precise time at which zero crossings occur is to use asmall transformer with an easily saturated iron core. Referring to FIG.10A, such the primary of such a transformer 80 is connected between thephase line and ground with an appropriately large resistor limiting thecurrent through the primary. Throughout most of the AC cycle on thephase 1 line, the core will remain saturated, except for a very shortperiod when the voltage waveform crosses zero. While the core issaturated, the output voltage on the secondary will be zero. When thecore comes out of saturation at the zero crossing, a pulse or blip willappear on the secondary marking the precise location of the zerocrossing, as illustrated in FIG. 10B.

Rectification with Step-down Transformation

The conversion of power from AC to DC is typically accomplished using arectification bridge in concert with other active and discretecomponents. The most common bridge configurations are half-wave,full-wave and six-phase, with the latter producing the most refinedoutput voltage. Less common is the twelve-phase configuration, which canbe accomplished by placing two six-phase rectifiers in series. Thetwelve-phase system minimizes output voltage ripple by increasing thefrequency at which power is delivered to the load. In high currentapplications where the output voltage is relatively low (<50 v),half-wave rectification is used because the inherent losses are lower.

The above-described SDR systems are regulated high power AC to DCconverters. The relatively high operating frequency and continuous powertransfer produce a ripple-free output voltage that can be effectivelyregulated by varying the rate of conversion. The conversion processcontinuously draws current from the source thereby eliminating reactivepower generation.

However, the SDR systems depicted in FIGS. 5, 7 and 8, have losses thatare even higher than those found in a full-wave bridge rectifier. As inthe full-wave bridge rectifier, the above-described SDR systems also usetwo solid state devices (i.e., SCR's) in series: one for the resonantcharge cycle and the second for the discharge cycle. Unfortunately, theSCR's, which are typically multijunction devices, have much largerforward voltage drops than the single junction diodes that are used inthe conventional full-wave bridge rectifier (e.g. 2 volts versus 0.7volts). In low voltage applications where the ratio of the operatingvoltage to the SCR forward voltage drop to (V_(o) /V_(f)) is small, thelosses can become significant. In applications such as aluminumproduction, electro-plating or copper refinement where high currents atvoltages less than 50 v are required, thus a modified SDR configurationwould be more suitable to reduce the impact of the losses on systemefficiency.

In general, the modified SDR system includes a front end which performsthe sequential discharge functions at high voltage levels and itincludes an output stage which uses a small, high frequency transformerto step down the voltage to the required low voltage level. This greatlyimproves the overall system efficiency by increasing the V_(o) /V_(f)ratio of the sequential discharge section of the circuit. The modifiedSDR system has an efficiency similar to that of the standard half-waverectifier while eliminating the need for an AC power transformer. Thefront end which performs the sequential discharge appears as a resistiveload to the grid. Thus, it exhibits of the previously described benefitsof SDR including harmonic free rectification and producing a power flowof unity power factor.

An illustrative configuration is shown in FIG. 11. As before, there arethree capacitors, C₁, C₂, and C₃, each of which is charged from somepower source, e.g. a three phase line (not shown). The charging circuitfor each capacitor might be a corresponding different PCS module or itmight be a simple resonant charging circuit, such as is illustrated inFIG. 8. In the latter case, each capacitor C₁, C₂ and C₃ is resonantlycharged by an SCR and inductor in series. The resulting voltage on eachcapacitor will be twice the instantaneous voltage of input line and itwill have the same polarity as that instantaneous line voltage. When theresonant charging is complete, the capacitors are sequentiallydischarged in order of their absolute voltage levels, as has beendescribed previously.

In the circuit of FIG. 11, the capacitors are discharged through acoupling pulse transformer 100 into a shared output inductor, L_(out).Transformer 100 has two primaries 102(a) and 102(b) and it has twosecondaries 104(a) and 104(b). Each of the dual secondaries 104(a) and104(b) is connected to inductor L_(out) through a corresponding one oftwo output diodes D_(a) and D_(b), which select the positive voltageoutput polarity. The rest of the output section is as previouslydescribed. It includes a free-wheeling diode D_(fw) and a low passoutput filter section including L_(filter), C_(f1), and C_(f2).Free-wheeling diode D_(fw) assures that any energy remaining in theoutput inductor L_(out) is transferred to the load following the lastcapacitor discharge and it also prevents the voltages across thecapacitors from reversing after they are discharged to zero volts duringthe discharging cycle.

An array of SCR's coupling the capacitors to the transformer 100 steerthe discharge of each capacitor to the appropriate one of the twoprimaries 102(a) and 102(b) of transformer 100, depending upon thepolarity of the voltage on the capacitor that is being discharged anddepending upon the direction of the magnetic flux within the core oftransformer 100 from a preceding discharge cycle. Four SCR's (namely,SCR_(1a+), SCR_(1a-), SCR_(1b+), and SCR_(1b-)) provide separatedischarge paths from capacitor C₁ to transformer 100. SCR_(1a+) is usedto discharge a positively charged C₁ through primary 102(a); SCR_(1b+)is used to discharge a positively charged C₁ through primary 102(b);SCR_(1a-) is used to discharge a negatively charged C₁ through primary102(a); and SCR_(1b-) is used to discharge a negatively charged C₁through primary 102(b). A corresponding set of SCR's, which are labeledin a similar manner, are used steer the discharge of capacitors C₂ andC₃.

A control module (not shown, but previously described) establishes thetriggering sequence which assures proper transformer flux reversal fromone discharge cycle to the next. The circuit of FIG. 11 permits the useof three-phase input power directly, and eliminates the need for both aAC step-down transformer and a polarity inverting transformer.

Note that the use of the dual primary--dual secondary transformer allowsone to reverse the magnetic flux in the core from one triggeringsequence to the next. This means that an even smaller transformer can beused without fear of saturating its core during operation.

An example of a triggering sequence will now be presented in detail tofurther illustrate the operation of the circuit shown in FIG. 11.Assume, for purposes of this example, that the three capacitors C₁, C₂and C₃ are being charged from a three-phase 440 V, 60 Hz AC line andthat the trigger rate is 48 times per cycle or 2,880 times per second.The voltage on each capacitor at the end of each charging cycle can bedetermined by the following equations:

    V.sub.c1 =2×A sin(ωt)

    V.sub.c2 =2×A sin(ωt+2π/3)

    V.sub.c3 =2×A sin(ωt-2π/3)

where "A" is the AC input voltage amplitude of 392 volts.

Table II shows capacitor voltages vs. time and it presents thetriggering sequence over an angle of 60 degrees. The table has eightentries separated in time by 7.5 electrical degrees, or every 0.347msec. The capacitor charge voltage and polarity is shown in columns 2through 4. Column 5 shows the capacitor discharge sequence, and column 6shows the SCR triggering sequence.

                  TABLE II                                                        ______________________________________                                        Time  V.sub.c1 V.sub.c2                                                                              V.sub.c3                                                                             Capacitor                                                                            Triggering                               (msec)                                                                              (Volt)   (Volt)  (Volt) Sequence                                                                             Sequence                                 ______________________________________                                        0.174  51.3    651.8   -703.0 3, 2, 1                                                                              3b-, 2a+, 1a+                            0.521 152.9    589.4   -742.2 3, 2, 1                                                                              3a-, 2b+, 1b+                            0.868 251.9    516.9   -768.8 3, 2, 1                                                                              3b-, 2a+, 1a+                            1.215 346.7    435.5   -782.2 3, 2, 1                                                                              3a-, 2b+, 1b+                            1.563 435.5    346.7   -782.2 3, 1, 2                                                                              3b-, 1a+, 2a+                            1.910 516.8    252.0   -768.8 3, 1, 2                                                                              3a-, 1b+, 2b+                            2.257 589.3    153.0   -742.3 3, 1, 2                                                                              3b-, la+, 2a+                            2.604 651.7     51.3   -703.1 3, 1, 2                                                                              3a-, 1b+, 2b+                            ______________________________________                                    

To understand how to interpret Table II, look at the first row wheretime equals 0.174 msec. A charging cycle occurring at this point in theinput voltage cycle, charges each of the capacitors to the voltagesshown in the columns labeled V_(c1), V_(c2), and V_(c3), Thus, at theend of the first charging cycle, the voltages on C₁, C₂, and C₃ are+51.3, +651.8, and -703.0, respectively. Since the magnitude of thevoltage on C₃ is largest and the magnitude of the voltage on C₁ issmallest, the discharge sequence will be 3-2-1, as indicated in thecolumn which is entitled "Capacitor Sequence". Since C₃ is charged to anegative voltage, either SCR_(3a-) or SCR_(3b-) must be used todischarge it through coupling transformer 100. In this case, the choicewas SCR_(3b-), as indicated in the column entitled "TriggeringSequence". Once the voltage across C₁ reaches zero volts, C₂ isdischarged through SCR_(2a+), followed by the discharge of C₁ throughSCR_(1a+). Notice that the SCR's that are selected to steer thedischarge are selected to keep the magnetic flux in the transformer coregoing in the same direction throughout the entire discharge sequence.

At the end of the discharge sequence the voltages on the capacitors willbe zero. During the next charging cycle, which occurs at T=0.521 msec,the capacitors will be charged to the voltages shown in the second rowof Table II. Since C₃ again has the largest voltage and C₁ the smallest,the discharge sequence will be the same as before, namely, 3-2-1. Thistime, however, the SCR's are selected so as to reverse the magnetic fluxin the transformer core as compared to the previous discharge cycle.Thus, to discharge C₁ instead of triggering SCR_(3b), the control moduletriggers SCR_(3a-). When V_(c1) reaches zero, SCR_(2b+) is triggered todischarge C₂ and then SCR_(1b+) is triggered to discharge C₁.

By adding a second bank of capacitors as shown in the dual inputconfiguration shown in FIG. 12, we can effectively double the powerthroughput of the system. In this configuration, there are two banks ofcapacitors, an upper bank labeled "a" and a lower bank labeled "b". Theupper bank includes capacitors C_(1a), C_(2a), and C_(3a), each of whichis charged from a different phase of a three phase input grid. The lowerbank includes capacitors C_(1b), C_(2b), and C_(3b), each of which isalso charged from a different phase of a three phase input grid. Thecapacitors are grouped in pairs (e.g. C_(1a) and C_(1b)), each pairbeing charged from the same phase of the input grid. As one capacitor ofa pair is being charged, the other capacitor of that pair is beingdischarged.

Each of the capacitors in the upper bank is connected to an upperprimary 102(a) of coupling transformer 100 through two SCR's that arearranged in parallel but with their polarities reversed with respect toeach other. For example, C_(1a) is connected to upper primary 102(a)through SCR_(1a+) which when triggered allows current to flow fromcapacitor C_(1a) to upper primary 102(a), and through SCR_(1a-) whichwhen triggered allows current to flow from upper primary 102(a) tocapacitor C_(1a). SCR_(1a+) is used to discharge capacitor C_(1a) whenits voltage is positive and SCR_(1a-) is used to discharge capacitorC_(1a) when its voltage is negative. The discharge circuits forcapacitors C_(2a) and C_(3a) are arranged similarly and thus thecorresponding components in FIG. 12 are labeled in like fashion.

Similarly, each of the capacitors in the lower bank is connected to alower primary 102(b) of coupling transformer 100 through two SCR's thatare arranged in parallel but with their polarities reversed with respectto each other.

This circuit configuration greatly improves the utilization of thethyristors by allowing the first set of capacitors to be charged fromthe input grid during the discharge cycle of the second set. It alsoallows the operating frequency to be about twice that of theconfiguration of FIG. 11. If the operating frequency is doubled, thisreduces the filter requirements and lessens the total cost per unitpower throughput.

In the dual input configuration, each pair of capacitors (e.g. C_(1a)and C_(1b)) shares an input filter, and all capacitors may share anoutput transformer, output diodes and the output filter. Thus, thisconfiguration also has the effect of lowering the overall system cost.

The doubled operation is shown in Table III. As can be seen, thecharging rate and power throughput has been increased by a factor oftwo. The charging and discharging sequence is identical to than of TableII, except that the rate has been increased.

                  TABLE III                                                       ______________________________________                                                                      Capacitor                                       Time  V.sub.c1 V.sub.c2                                                                              V.sub.c3                                                                             Discharge                                                                            Triggering                               (msec)                                                                              (Volt)   (Volt)  (Volt) Sequence                                                                             Sequence                                 ______________________________________                                        0.174  51.3    651.8   -703.0 3b, 2a, 1a                                                                           3b1, 2a+, 1a+                            0.347 102.3    621.9   -724.1 3a, 2b, 1b                                                                           3a-, 2b+, 1b+                            0.521 152.9    589.4   -742.2 3b, 2a, 1a                                                                           3b-, 2a+1b+                              0.694 202.9    554.3   -757.1 3a, 2b, 1b                                                                           3a-, 2b+, 1b+                            0.868 251.9    516.9   -768.8 3b, 2a, 1a                                                                           3b-, 2b+, 1a+                            1.042 300.0    477.2   -777.1 3a, 2b, 1b                                                                           3a-, 2b+, 1b+                            1.215 346.7    435.5   -782.2 3b, 2a, 1a                                                                           3b-, 2a+, 1a+                            1.389 391.9    392.0   -783.8 3a, 2b, 1b                                                                           3a-, 2b+, 1b+                            1.563 435.5    346.7   -782.2 3b, 1a, 2a                                                                           3b-, 1a+, 2a+                            1.736 477.2    300.0   -777.1 3a, 1b, 2b                                                                           3a-, 1b+, 2b+                            1.910 516.8    252.0   -768.8 3b, 1a, 2a                                                                           3b-, 1a+, 2a+                            2.083 554.2    202.9   -757.2 3a, 1b, 2b                                                                           3a-, 1b+, 2b+                            2.257 589.3    153.0   -742.3 3b, 1a, 2a                                                                           3b-, 1a+, 2a+                            2.431 621.8    102.4   -724.2 3a, 1b, 2b                                                                           3a-, 1b+, 2b+                            2.604 651.7    51.3    -703.1 3b, 1a, 2a                                                                           3b-, 1a+, 2a+                            2.778 678.8    0.0     -678.9 3a, 1b, 2b                                                                           3a-, 1b+, 2b+                            ______________________________________                                    

Notice that in Table III the time steps have been reduced and there isreference to capacitor banks a and b (for the upper or lower capacitors,respectively).

The trigger timing of the second and third output SCR's, in the sequenceshown in Table III, is such that no energy remains in the capacitors andno free-wheeling current flows until the last capacitor is discharged.During normal operation, the maximum free-wheeling current is only afraction of the total output current. The free-wheeling diode's functionis not only to facilitate the full capacitor energy transfer but also topermit output voltage regulation.

The losses in the output diode of a standard half-wave rectificationsystem are identical to those in the free-wheeling diode in a SDRsystem. For low output voltage systems the dominating losses occur inthe output diodes. In either configuration, the total output current hasto flow through one of the two diodes. The SDR system overcomes theinherently greater losses by operating at a higher voltage, thusminimizing the current through the switches. The losses in the thyristorare inversely proportional to the input voltage. If the input current isa factor of 20% to 50% higher than the output voltage, the thyristorsincrease the effective rectification losses by less than 10%. A largeSDR installation could efficiently operate directly off the 11 kVsubstation voltage, thereby reducing the thyristor losses to aninsignificant value.

An SDR system operating at a frequency of 1.5 kHz will be able to use amuch smaller step-down transformer with a smaller amount of corematerial than can a system that operates at 60 Hz. The cost savingsrealized by using a significantly smaller transformer can be used toimprove the quality of the core, improving the overall system efficiencywithout effecting the overall cost. This will, in part or completelycancel the thyristor losses, depending on the detailed operatingconditions. Also, it should not be forgotten that SDR systems do notrequire any harmonic filtering or VAR compensation, therefore, thelosses of these components are also eliminated.

The triggering sequences given in Tables II and III are such that theflux in the core is not reversed during a single discharge sequence.This requires a minimum core size based on the full duration of adischarge sequence. The core flux is reversed for the next sequentialdischarge, completing the transformer output cycle.

The core size can be reduced even further with the same components byreversing the core flux during each output sequence. Selecting acharging and triggering sequence as shown in Table IV meets thisobjective. The core flux is typically alternated for the first pulse ofeach consecutive discharged sequence, while the current and flux for thesecond and third discharge of the sequence is reversed from that of thefirst discharge. This results in a nearly complete core reset for eachsequential output. The net result is an additional reduction of the coresize over the cores with the discharge sequence shown in Table II andTable III.

                                      TABLE IV                                    __________________________________________________________________________                    Capacitor                                                     Time                                                                              V.sub.c1                                                                          V.sub.c2                                                                          V.sub.c3                                                                          Discharge                                                                          Triggering                                                                           Flux                                              (msec)                                                                            (Volt)                                                                            (Volt)                                                                            (Volt)                                                                            Sequence                                                                           Sequence                                                                             Direction                                         __________________________________________________________________________    0.174                                                                             51.3                                                                              651.8                                                                             -703.0                                                                            3a, 2a, 1a                                                                         3a-, 2a+, 1a+                                                                        up down down                                      0.347                                                                             102.3                                                                             621.9                                                                             -724.1                                                                            3b, 2b, 1b                                                                         3b-, 2b+, 1b+                                                                        down up up                                        0.521                                                                             152.9                                                                             589.4                                                                             -742.2                                                                            3a, 2a, 1a                                                                         3a-, 2a+, 1a+                                                                        up down down                                      0.694                                                                             202.9                                                                             554.3                                                                             -757.1                                                                            3b, 2b, 1b                                                                         3b-, 2b+, 1b+                                                                        down up up                                        0.868                                                                             251.9                                                                             516.9                                                                             -768.8                                                                            3a, 2a, 1a                                                                         3a-, 2a+, 1a+                                                                        up down down                                      1.042                                                                             300.0                                                                             477.2                                                                             -777.1                                                                            3b, 2b, 1b                                                                         3b-, 2b+, 1b+                                                                        down up up                                        1.215                                                                             346.7                                                                             435.5                                                                             -782.2                                                                            3b, 2b, 1b                                                                         3b-, 2b+, 1b+                                                                        up down down                                      1.389                                                                             391.9                                                                             392.0                                                                             -783.8                                                                            3b, 2b, 1b                                                                         3b-, 2b+, 1b+                                                                        down up up                                        1.563                                                                             435.5                                                                             346.7                                                                             -782.2                                                                            3a, 1a, 2a                                                                         3a-, 1a+, 2a+                                                                        up down down                                      1.736                                                                             477.2                                                                             300.0                                                                             -777.1                                                                            3b, 1b, 2b                                                                         3b-, 1b+, 2b+                                                                        down up up                                        1.910                                                                             516.8                                                                             252.0                                                                             -768.8                                                                            3a, 1a, 2a                                                                         3a-, 1a+, 2a+                                                                        up down down                                      2.083                                                                             554.2                                                                             202.9                                                                             -757.2                                                                            3b, 1b, 2b                                                                         3b-, 1b+, 2b+                                                                        down up up                                        2.257                                                                             589.3                                                                             153.0                                                                             -742.3                                                                            3a, 1a, 2a                                                                         3a-, 2a+, 2a+                                                                        up down down                                      2.431                                                                             621.8                                                                             102.4                                                                             -724.2                                                                            3a, 1b, 2b                                                                         3b-, 1b+, 2b+                                                                        up down down                                      2.604                                                                             651.7                                                                             51.3                                                                              -703.1                                                                            3a, 1a, 2a                                                                         3a-, 1a+, 2a+                                                                        up down down                                      2.778                                                                             678.8                                                                             0.0 -678.9                                                                            3b, 2b                                                                             3b-, 2b+                                                                             down up                                           __________________________________________________________________________

SDR systems have several advantages over standard half-waverectification systems. The output can be precisely regulated, and onecan provide short circuit protection and fast disconnect capability.Should a fault occur, the system can be shut down in less than onemillisecond. Only the residual energy stored in the filter capacitor canrush into the fault. With the typical energy stored in the filtercapacitors this is generally less than the energy used in 2.5milliseconds.

To see how the SDR system stacks up against a system of similarperformance, one could compare it with a phase-control regulated systemwith regulated output and fault protection. A phase-control regulatedsystem increases the half-wave system losses by the losses of thephase-control thyristors. Assumed to be on the input side of the ACstep-down transformer, the additional losses equal that of the SDRthyristors and make the total solid-state device losses for both systemsidentical. Furthermore, the phase control devices produce additionalharmonics that need to be neutralized with additional and largerharmonic filters.

Using the SDR technology will significantly reduce transformer size, aswell as system size and volume. The transformer couplings, inconjunction with sequential discharging, permits several differentelectrical configurations. Multiple input transformer windings may beused. For example, one is not restricted to use the phase-to-neutralconfigurations implied in FIGS. 11 and 12. Instead, one may use thephase-to-phase input voltage directly in conjunction with isolatedtransformer windings. This opens up additional options and, for someapplications, improves the performance even further.

In addition, full wave rectification may replace the half waverectification if the required output voltage level is higher.

FIG. 13 shows a three-phase configuration that permits charging directlyfrom a three-phase grid using a phase-to-phase input. Six capacitors,labeled C_(1a), C_(1b), C_(2a), C_(2b), C_(3a), and C_(3b), make up twoseparate sets of three capacitors that can be charged and dischargedalternately, as described above. The circuit of FIG. 13 uses three dualprimaries 110(1a) and 110(1b), 110(2a) and 110(2b), and 110(3a) and110(3b), and one dual secondary 112(a) and 112(b), permitting fluxreversal for each capacitor discharge within a discharge cycle. Thesystem is configured so that each pair of capacitors (i.e., C_(1a) andC_(1b), C_(2a) and C_(2b), and C_(3a) and C_(3b)) has in its output lega corresponding pair of dual primaries which makes it possible toreverse the flux between alternate discharges, as previously describedin connection with FIG. 12. In each case, the shared output inductorL_(out) is the one being `charged`.

Note that FIG. 13 also includes the input charging circuits for all ofthe capacitors. The power from each phase is filtered by a low passfilter which, in this example, includes a series inductor L_(f) and ashunt capacitor C_(f). Each of the capacitors is then resonantly chargedthrough an inductor L_(INi) (where I=1,2,3). The charging cycles foreach capacitor are controlled by a pair of parallel SCR's. thedischarging circuits are the same as those which were illustrated inFIG. 12, except that each pair of capacitors (e.g. C_(1a) and C_(1b)) isconnected to a different dual primary instead of the same dual primary(e.g. in the case of C_(1a) and C_(1b) it is dual primaries 110(1a) and110(1b)).

The discharging is controlled so that a first set of capacitors,consisting of C_(1a), C_(2a), and C_(3a), may use one set of threeprimary windings during one discharge phase while a second set ofcapacitors, consisting of C_(1b), C_(2b), and C_(3b), uses the other setof three primary windings during the next discharge phase. In this way,the voltage polarity is reversed on each dual winding per charge anddischarge cycle. Typically, the core would see an operation similar tothat covered in Table IV.

Finally, a transformer, configured as in the previous operation, wouldcreate a complete flux reversal only between each charge and dischargecycle. This would correspond to the operation as described in Table III.Depending on the operating conditions and component characteristics,each configuration (i.e., the circuits of FIGS. 11, 12, and 13) may havean advantage over the other two. The second operating configuration(i.e., FIG. 12) would permit use of a smaller total core volume, whilethe first and third configurations (i.e., FIGS. 11 and 13) might be moreappropriate for high power throughput requirements.

The transformer-coupled configuration permits isolation between theprimary and secondary and increases system flexibility. This permits thesecondary to float and permits the use of the phase to phase voltage ora dual input power system. In addition, a standardized input sectionwith optimum design might be developed for many different output voltagerequirements. Only the output transformer and filtering section need tobe modified for the different voltage requirements. No problems canoccur while parallel modules are operational, since the power throughputsharing can be precisely controlled.

In summary, the SDR can be adopted to any voltage range of interest withhigh efficiency with the use of a high frequency output transformer.This permits the sequential control to be performed at a high voltage tominimize the thyristor losses. In addition, this technique produces areduction in cost, losses, volume and weight of the AC step-downtransformer.

Using Transformer Input/Output with the PCS

Step-Up Configurations:

As indicated in the earlier patent, an advantage of the PowerConditioning System (PCS) is that it requires no transformer or AC linkto change the voltage. Eliminating AC transformers from the powerdistribution system significantly reduces complexity and cost, increasesefficiency, and most importantly appeals to the technical community.However, as suggested above, there may be instances in which it isbeneficial to also use transformers in the PCS system.

For example, note that the PCs losses are mainly switching losses fromthe thyristors. It can be shown that the loses (i.e., η) areapproximately equal to:

    η(%)=100×2×(V.sub.f /V.sub.o)×(N+2);

where N is the transformation ratio of the PCS, V_(f) is the forwardvoltage drop of the switch, and V_(o) is the switch voltage operatinglevel. The advantage of a thyristor is that devices up to V_(o) =12,000volts are available for efficient high voltage operation. Since thetypical thyristor has a forward voltage drop of V_(f) =2.0 volts, theefficiency is better than 99.5% for a transformation ratio on the orderof N=10. The problem, however, is that thyristors, both SCRs and GTOS,are four layer devices with a voltage drop that is independent of theoperating voltage. Therefore, it follows that if we use a thyristor forlow voltage operation, such as 10 volt solar or fuel cells or 110 voltconsumer power, the ratio (V_(f) /V_(o)) is high, thus lowering theoverall efficiency of the system. If lower input voltages are used togenerate higher output voltages, the transformation ratio N also needsto be larger, thereby causing an additional reduction in efficiency.With such losses, the PCS would have limited appeal in consumer marketsand some industrial markets in comparison o alternative moreconventional approaches. However, by adding a pulsed transformer to thePCS that operates at high frequencies, the efficiencies can besignificantly improved and the overall transformation ratio can also beincreased.

In this hybrid configuration, which is used for medium power, lowervoltage operation, the pulsed transformer can be either added to theinput or the output of the PCS. If the initial voltage is in the lowvoltage range and it must be stepped up to a higher voltage, thetransformer would be added to the input side. If the input voltage ishigh and it must be stepped down, then the transformer would be added onthe output side. To illustrate this approach, I will first describe aPCS step-up circuit using a modified low voltage input, as show in FIG.14.

The circuit includes a basic step-up PCS module 200 connected to apulsed transformer input section 202. The basic PCS circuit is a 1:6voltage step-up configuration constructed as described in U.S. Pat. No.5,270,913, with the exception that a diode (D_(o)) is used in place ofan SCR on the input side of the PCS module.

Pulsed transformer input section 202 includes a transformer T_(IN)configured to step-up the input voltage by a moderate amount. In thedescribed embodiment, transformer T_(IN) includes multiple (e.g. three)primary input windings 204(1), 204(2), and 204(3) operated in paralleland three secondary windings 206(1), 206(2), and 206(3) connected inseries. Depending on the magnetics design, one may either use a separatetransformer core for each primary input winding or a single core withmultiple primary input windings. In the illustrated embodiment, threecores each with an associated secondary winding are used. In thisconfiguration, the effective transformer step-up ratio is the product ofthe number of cores times the turns ratio of each transformer section.

Transformer input section 202 also includes three input switches labeledS₁, S₂, and S₃, each of which controls the power to a corresponding oneof the primary windings. This configuration permits good current sharingcontrol and full average current rating utilization. Transformer inputsection 202 steps-up the input voltage before it is applied to the PCScharging system. This permits us to operate the SCR's (e.g. thyristors)in the PCS module at a higher voltage and thus achieve a higherefficiency, since both the (V_(f) /V_(o)) ratio and the PCSmultiplication of N (N=6) is kept low.

Solid state switching devices have been developed to operate at the lowto medium voltage ranges with a significantly lower forward voltage dropthan is found in thyristors. Examples of devices which can be used forthe switches S₁ -S₃ are power FET's, IGPT's and, depending upon theapplication, even conventional bipolar transistors.

The pulsed input transformer is shown in an equivalent configuration inFIG. 15. It includes an input inductance L_(a), an output inductanceL_(b), and a shunt inductance Ls. Typically, shunt inductance L_(s) islarge so that, from an operational point of view, the charginginductance as seen by the transformer input section consists of threeinductors in series: L_(a), L_(b), and L_(in). The operation of thecircuit includes a charge cycle, an inversion cycle, and a dischargecycle. During the charge cycle, capacitors C₁ -C₆ of the PCS module areall charged to the same voltage from the power source. During theinversion cycle, the voltages on capacitors C₂, C₄, and C₆ are invertedwith the aid of inductors L₁, L₂, and L₃, respectively. And during thedischarge cycle, the charge that was stored in the series connectedcapacitors C₁ -C₆ is injected at the transformed voltage into a loadthrough output inductor, L_(out).

Charging is started by simultaneously closing the low voltage inputswitches S₁, S₂, and S₃ and triggering the return current thyristorsSCR₁, SCR₂, and SCR₃. Assuming that the transformer ratio is N, theneach of the capacitors will be resonantly charged through a resonantcharging inductor L_(IN) to 2×3×N×V_(IN). Note that diode D_(o) preventscapacitor C₁ from discharging through the secondary pulse transformer.

In this voltage step-up mode, the capacitor string is charged in analternating sequence such that each adjacent capacitor has the oppositevoltage polarity. The voltage of the capacitor string, when fullycharged, is thus zero. The charging period is defined by the inputcharging inductance (i.e., L_(IN) +L_(a) +L_(b)) and the parallelcapacitor value (i.e., six times C₁, assuming the capacitors are all ofthe same value).

With SCR₁, SCR₂, and SCR₃ recovered, the triggering of SCR₄, SCR₅, andSCR₆ starts the inversion cycle. The purpose of the step-up inversioncycle is to change the polarity of half of the capacitors in thecapacitor string such that all of the capacitors have the same polarity.In the circuit shown in FIG. 14, the polarity of capacitors C₂, C₄, andC₆ are reversed to generate a positive output voltage. The SCR's areimportant for the inversion process because they prevent the currentfrom ring back through the inductor and allow the extraction of theinverted energy in an efficiently and controlled fashion.

At the conclusion of the inversion cycle, the total voltage across thestring of series connected capacitors (i.e., C₁ through C₆) will be sixtimes the voltage across C₁ (or twelve times the output voltage of thetransformer). The positive voltage across the C₁ to C₆ capacitor stackcan then be switched to the output by another SCR (i.e., SCR_(out)).

Note that as previously described, the sequence of charging, inversion,and discharging occurs multiple times per second, e.g. 1-2 kHz orhigher. Thus, if the voltage source is a 60 Hz AC voltage source, thenV_(IN) to transformer input section 202 is the instantaneous voltage ofthe AC voltage waveform at the time at which the charge cycle. Thecomponents are selected so that the charge cycle, the inversion cycle,and the discharge cycle can each complete in a short time, e.g. shorterthan 1 ms.

Assuming that we start out with a low voltage (V_(in)) from a lowvoltage power source such as solar cells, storage batteries or fuelcells, the input voltage will be significantly lower than 100 volts andthe required step-up ratio that is required will typically be muchhigher than 6. If only a PCS module were to be used to handle the entiretransformation, the low input voltage and the high step-up ratio that isrequired would result in poor efficiency. However, by using the pulsedtransformer input section to provide some of the step-up transformation,the overall efficiency of the circuit can be greatly improved.

Additional windings may be used on each core to implement additionalinput from separate voltage sources or sources of opposite polarity. Anexample of such an implementation is shown in FIG. 16. In that case, adual polarity source, identified as -Input and +Input, is used. In thiscase, transformer input section 212 includes a pulse transformer withtwo primary windings 214(1) and 214(2) wound in opposite directionsaround a common core. A secondary winding input 216 is connected to theinput side of the PCS module as previously described. In all otherrespects, the circuit is the same as that shown in FIG. 14 and thus theother components are similarly identified.

To utilize both polarities of the AC input waveform in the basic PCSmodule, it is necessary to add thyristors in parallel (but of oppositepolarity) with the thyristors in the charging and inversion circuits. Ascan be seen, in the embodiment of FIG. 16, the second set of thyristorsis not necessary. Thus, this modified circuit with the dual polarityinput section significantly reduces the parts count and cuts theprobability of thyristor failure nearly in half, in comparison with abasic PCS module without a transformer input section. In addition, ifdiodes are be used for the PCS interstage isolation components, such asD₁ and D₂ in FIGS. 14 and 16, additional benefits are obtained. First,the use of a high voltage diode with only one junction for a thyristorwhich has three junctions, reduces the losses in those locations wherethis substitution is possible. Secondly, the control system issimplified, since diodes require no triggering. And finally, the cost isreduced, since diodes with similar power ratings are less expensive.

As indicated above, each input may have several switches and coresconnected in parallel. This concept may be extended to multiple inputsources in polarity and/or AC phases, and to multiple AC sources. Inaddition, the capacitor charging voltage may be regulated by using inputswitch on/off control, of specific benefit for lower power flow andinput/output filter optimization.

Step-Down Configurations:

A transformer may also be used in a step-down configuration, as shown inFIG. 17. In this example, a PCS module 300, which is configured as astep-down module, is used as a high voltage input section to thecircuit. An additional step-down ratio is obtained by then using alow-loss, output step-down pulse transformer(s) 302 at the low voltageend. Transformer 302 include a primary 304 and three secondaries 306(1),306(2), and 306(3). One side of each secondary is connected to groundand the other side of each secondary is connected through acorresponding one of low loss, low voltage switches (S₁, S₂, and S₃) tothe output node 308. In this example, the step-down ratio from theprimary to each secondary is 1/N; thus the overall step-down ratio ofthe transformer is 1/3N.

As before, there is a charge cycle, an inversion cycle and a dischargecycle. During the charge cycle, SCR_(IN) is triggered and the seriesconnected chain of capacitors C₁ -C₆ is resonantly charged throughL_(IN) Up to 2V_(INPUT). During the inversion cycle, SCR₁, SCR₂, andSCR₃ are simultaneously triggered to enable inductors L₁, L₂, and L₃ toinvert the voltages across each of capacitors C₂, C₄, and C₆,respectively. Finally, during the discharge cycle, SCR₄, SCR₅, and SCR₆are triggered to discharge the capacitors, which are now configured inparallel arrangement through diodes D₁, D₂, and D₃. The discharge isthrough output inductor L_(OUT) into the primary 304 of transformer 300.Simultaneously with the triggering of SCR₆, switches S₁ through S₃ arealso turned on to allow the injection of the energy from the output oftransformer 300 to be delivered to the output node, which might by apower distribution point or a terminal of a load (not shown).

As in the case of previous embodiments, the pulsed operation (consistingof a charge cycle, an inversion cycle, and a discharge cycle, occursmany times per second, e.g. 1-2 kHz.

Switches S₁ through S₃ can be implemented by any one of a wide selectionof conventional switching devices such as, power FET's, IGPT's, IPET's,conventional bipolar transistors, thyristors or other semiconductorswitching devices. Alternatively, for many applications (e.g.rectification or injection into a DC load) simple diodes may be usedinstead of switches. One advantage of using diodes is that using themsimplifies the control circuitry which operates the switches within thecircuit.

Again, by operating the PCS module in this way at the higher voltages,we are able to avoid that region of operation where its efficiencybegins to suffer due to the relatively high forward voltage drops of theSCR's in the module. In other words, as before we achieve the higherefficiencies associated with high voltage operation. In addition, byrelying on the transformer to achieve part of the overall step downratio that is required, we also avoid multiplying the losses within thePCS module by the full amount of the step-down ratio.

The output section utilizes for the discharge a transformer and aninductor in series. These two components define the discharge period andthe effective inductance for the resonant discharging mode. The inductormay also be placed in the output of the transformer or its effectedvalue may may be incorporated into the transformer during its design. Itfollows that the output section can be coinfigured in such a way thatthis section may be shared by several modules to permit sequentialdischarging for the various applications and configurations described inan earleir section herein. In fact, the transformer coupled input, thePCS control, and the inversion functions, as well as the transformercoupled output section may be selectively combined into one module. Byadding a completely or partially shared output section, multiple suchmodules may be combined to permit dual or multiple resonant dischargeoperations as previously described. Such modules may be usedbeneficially in any of the circuit applications covered herein ordescribed in the earlier patent.

It should be noted that the input voltage to the circuits shown in FIG.14-17, as with the previously escribed embodiments, can be either AC orDC. This should be readily apparent from the fact that the circuit isbeing operated in a pulsed mode which samples the voltage of thewaveform many times per second.

Real and Reactive Power Control

In U.S. Pat. No. 5,270,913, filed Apr. 6, 1992, entitled "Compact andEfficient Transformerless Power Conversion" and incorporated herein byreference, I disclosed that energy can be extracted and injected into aterminal using resonant charging and discharging. In U.S. patentapplication Ser. No. 08/494,236 filed Jun. 23, 1995, entitled"Sequential Discharge and Its Use for Rectification," and alsoincorporated herein by reference, I disclosed a technique that permitsthe controlled extraction of energy and power from a multi-phase ACsystem to produce harmonic free rectification. I have also configured acircuit that permits the inverse process of reconstructing a multi-phasesystem either from a DC potential or from an AC source. I utilizedmultiple interactions of a capacitor with one or more terminals topermit the control of real and reactive power extraction and injection.Below, I give the specific mathematical derivations as well as how toimplement the process with practical circuitry. The following topics arecovered with practical implementations:

a. Real power flow control

b. Reactive power flow control

c. Combined real and reactive power flow control

d. Harmonic power flow control

Mathematics of Power Control

In this section, I show that by proper selection of the initialconditions on the capacitors in the charge transfer circuits, it ispossible to control power flow into and out of the charge transfercircuit and to determine its character, i.e., what proportion of it isreal and what proportion of it is reactive. For this mathematicalpresentation, we assume a three phase system with a voltage on each ofthe three phases of: ##EQU6##

Referring to FIG. 18, it can be readily show that by charging acapacitor C through an inductor L from a voltage source of voltage V(t)and by controlling this charging with a switch, such as an SCR, thevoltage of the capacitor will be 2 V(t). By repeating this process at afrequency f; with f larger than ω/2π, we will be loading down thatterminal as if the load was resistive. This was demonstrated in myrectification system which was described above and in U.S. patentapplication Ser. No. 08/494,236. However, if we start out with aninitial voltage V₁ on the capacitor, after resonant charging thecapacitor voltage V_(f) will be as follows:

    V.sub.f =2V.sub.in -V.sub.i                                Eq. 2

This yields a change in the potential of the capacitor of ΔV=2(V_(in)-V_(i)). The change in the charge of the capacitor is CΔV and thus if werepeat this process at a frequency f, the current flow in or out of theterminal will be:

    I=ΔVCf=2Cf(V.sub.in -V.sub.i)                        Eq. 3

For the purposes of drawing any repetitive current waveform, we candefine the current in terms of a Fourier series, as follows: ##EQU7##with A₁ being the real current component I and B₁ being the reactivecurrent I₁. The component A_(n) is the harmonics amplitude for then^(th) harmonic with n>1. By combining Eq. 3 with Eq. 4, we cancalculate the initial voltage requirements for the capacitors in orderto draw or inject any desired current from the voltage terminal. Theresulting equation is as follows: ##EQU8## This can be done by eitheroperating at a constant frequency or by varying the interpulse duration,i.e., f=f(t), as long as this is reflected in Eq. 5.

Real Power Flow Control

With the voltage on the first phase given by the following equation:

    V.sub.a =V.sub.o sin (ωt)                            Eq. 6

we may solve specific problems. For example, we can generate a currentthat is in phase with the voltage:

    I(t)=I sin(ωt)                                       Eq. 7

and thereby achieve real power flow with no reactive component. First,we let I=I_(o) (1+γ), where I_(o) is the current amplitude and where γis a parameter that describes the amount of residual capacitor charge.To see that γ is indeed a fair representation of the amount of residualcharge, notice that Eq. 3 above can be rewritten as follows: ##EQU9##Thus, -γ corresponds represents V_(i) /V_(in), and is thus indeedproportional to the residual charge.

Substituting Eqs. 6 and 7 into Eq. 5, we find an expression for what theinitial voltage of the capacitor must be: ##EQU10## With the initialvoltage of the capacitor equal to zero, it follows that:

    I.sub.o =2CfV.sub.o,                                       Eq. 9

and thus

    V.sub.i (ωt)=-γV.sub.a (ωt)              Eq. 10

In other words,

    I(t)=2V.sub.o Cf(1+γ) sin(ωt)                  Eq. 11

In this case, the power throughput is equal to:

    P(t)=I(t)V.sub.in (t)

     =2Cf(1+γ)V.sub.o.sup.2 sin.sup.2 (ωt)         Eq. 12

     =P.sub.0 (t)(1+γ),

where P₀ (t)=2CfV_(o) ² sin² (ωt)

From Eqs. 11 and 12, it can be seen that the power throughput can becontrolled by simply controlling the initial voltage V_(i) on thecapacitor and without changing the frequency f.

The same applies for the other two phases such that the total throughputis independent of time. This can be seen by summing the power of allthree phases, which equals:

    P(t)=2Cf(1+γ)V.sub.o.sup.2 {sin.sup.2 (ωt)+sin.sup.2 (ωt-120°)+sin.sup.2 (ωt-240°)}.

The quantity in the brackets { } equals a constant, i.e., 3/2. Thus, thetotal power is not a function of time.

Also of importance is that the output can be varied over a large rangeand that the power flow can be bi-directional. This technique permitsone to transfer power from a lower voltage AC line to a higher AC line.

Reactive Power Flow Control

Assuming again that the voltages are as shown in Eq. 1, then reactivepower flow is represented by:

    I.sub.r (t)=I.sub.r cos(ωt)                          Eq. 13

Substituting I_(r) (t) into the right side of Eq. 5, one obtains##EQU11## or, equivalently: ##EQU12## where: ##EQU13## The total energyin all three capacitors is given by: ##EQU14## which is also independentof time.

Eqs. 13 and 16 show that one may produce both leading or lagging VAR.Again, this is produced without changing the frequency f. However, tochange the VAR, Eq. 17 makes it clear that the total energy must bechanged. This can be accomplished by drawing or dumping energy back intothe power source for one cycle.

The computation for the real and reactive power flow is given in thenext section. The VAR requirement can be changed immediately without achange of the total energy in the capacitors by simply changing thepulse repetition rate f.

In a practical device, however, we must actually control the system soas to draw real power since we have to compensate for component losses.

Real and Reactive Power Flow

I have shown that both the real and reactive power flow can becontrolled separately by controlling the initial capacitor voltage. Theycan also be controlled together. How to do this can be seen by lookingat an expression for current which contains both real and reactivecomponents as follows:

    I(t)=I.sub.o (1+γ) sin(ωt)+I.sub.r cos(ωt)Eq. 18

Using the approach described above, one obtains the following expressionfor the initial voltage that must be created on the capacitors prior toeach charge transfer cycle: ##EQU15## When one uses V_(i) (t)=Asin(ωt-β) for Eq. 19, one obtains: ##EQU16##

By taking the limit as γ-1, one obtains only the reactive term.Similarly, with I_(r) =0, one obtains the real power flow.

It should be understood that for a three phase system, the currentvoltage and residual voltage must be shifted by -120 and -240 electricaldegrees for the other two phases, respectively.

Power, VAR, and Harmonics

Power flow, harmonics correction, and VAR control can all be combined.This is done as follows. Assume that the current is given by:

    I(t)=I.sub.o (1+γ) sin(ωt)+I.sub.r cos(ωt)+I.sub.n sin(nωt)                                            Eq. 21

where I_(n) is the amplitude of the nth harmonic. Then, one proceedsthrough the same steps as described above and derives the followingrequirement for the initial voltage: ##EQU17## That is, Eq. 22 specifiesthe initial voltage condition that is required to control the realpower, VAR and the nth harmonic.

One may also proceed to control all of the harmonics along with the realpower by letting: ##EQU18## which yields: ##EQU19##

From a circuit point of view, it can also be readily shown that VAR andharmonics correction can be performed in a single device by letting:##EQU20## It then follows that the initial voltage must be: ##EQU21##With I_(r) and I_(n) given by measurements of the VAR and harmonics, thecorrection can be readily implemented.

The harmonic and VAR power per phase can be obtained by multiplying thecurrent by V(t)=V_(o) sin (ωt). If one proceeds with the other twophases, ##EQU22## it can again be seen that the total power flow is zeroand that the total energy in the combined capacitor does not change overtime unless I_(r) or I_(n) changes, assuming that n is a multiple of 3.(Note: For harmonics other than multiples of 3, energy must be stored.)It follows that if the frequency f is high, all harmonics, to a specificnumber, may be simultaneously corrected or induced.

If the frequency f is lower, corrections must be applied to take intoconsideration that the requirement for the next V_(i) at the correcttime when the charge interchange between the capacitor and the linetakes place.

In a practical device for VAR and harmonics generation, the circuit ofcourse has losses. To make up for these losses, a small additional termneeds to be added to Eq. 26. The real and reactive term then has theform of Eq. 20, while the harmonics term does not change.

To start such a Static VAR and Harmonics Generator, real power has to bedrawn off the grid to build up the capacitor voltages. This can beperformed in one charge cycle of over several AC cycles.

AC--AC Frequency Charger

The preceding mathematical analysis yields the voltage requirements forthe operation of various systems. FIG. 19 shows a practical circuit withwhich the above-described techniques can be implemented. The circuit ofFIG. 19 includes a rectification section 300 at the front end to producea DC output, a filter capacitor Cf receiving the DC output of therectification section, and a derectification section 302 on the back endto reconstruct three-phase AC from the DC voltage on Cf. The techniquefor operating this circuit relies in part on harmonic free rectificationand on derectification, which is described in detail below. Suffice itto say at this point that derectification is in essence the inverseprocess to rectification, i.e., it is rectification performed in reverseto generate an AC waveform, typically, but not necessarily from a DCsource. Note that if both the discharging process of the rectificationsection and the charging process of the derectification section aresynchronized, then filtering (i.e., capacitor Cf) is not required.

In the AC to AC frequency changer circuit of FIG. 19, there are threeinputs, each connected to a respective phase of a three phase AC linethrough a corresponding input filter 310, and there are three outputs,each connected to a respective phase of another three phase AC linethrough a corresponding output filter 312. In some of the subsequentcircuit diagrams, we may not always show the input and output filters,but it should be understood that such filters are present where and whenit would be appropriate to use them. In addition, since the design andconstruction of such filters is well know to persons of ordinary skillin the art, no further details about the filters will be provide here.

The rectification section 300 includes for each phase, a resonantcharging inductor Linj which is coupled through a pair of SCR's (i.e.,SCRinjp and SCRinjn, where j=1,2,3) to a corresponding charge storagecapacitor Cinj. The pair of SCR's is connected in parallel and withtheir polarities in opposite directions so that the corresponding chargestorage capacitor can be charged from a voltage source of eitherpositive or negative polarity. The capacitors are coupled to a filtercapacitor Cf through an output inductor Lo.

The derectification section 302 is basically the same as therectification section 300 except that it is arranged in reverse order.

I will be using the circuit of FIG. 19 and modifications of it toillustrate the use of residual voltage on both the input and outputcapacitors to show that we can control both the real and reactive powerflow on the input as well as on the output side. In a later section, Iwill describe a second technique that will permit the same functionswith a simpler circuit.

Input Power Control

First, I summarize the rectification process that was described aboveand in U.S. Ser. No. 08/494,236, but this time with two additionalfeatures. In this circuit, I use two three phase, common bridge circuits304 and 306, one at the output of the rectification section 300 tocharge the capacitor Cf to have the desired polarity and one at theinput of the derectification section 302 to charge the capacitors in thederectification section to the desired polarity. In FIG. 19, the SCR'slabeled SCRip and SCRin form the bridge circuit 304 on the rectificationside and the SCR's labeled SCRik and SCRis form the bridge circuit 306on the derectification side. The simultaneous charging or dischargingfrom or to a three phase grid is initiated by triggering the correctinput SCR (or other switches). By using the common bridge circuit, onedoes not need a neutral return. This permits the common capacitorconnection to float. In addition, the use of the common bridge circuitalso eliminates the need for an inversion circuit. (Note that aninversion circuit is described in U.S. Pat. No. 5,270,913, elsewhere inthis description, and in U.S. patent application Ser. No. 08/494,236.)That is, Cf can be charged to a positive voltage regardless of whetherthe source is positive or negative. For example, if phase 1 is positive,capacitor Cf can be charged positive simply by triggering both SCR1p andSCRnp; and if phase 1 is negative, capacitor Cf can be charged positivesimply by triggering both SCRin and SCRnn. However, there is a price topay for using the bridge circuit, namely, higher voltage swings on thethyristors.

Note that the SCR's in the circuit of FIG. 19, and the switches in theother circuits described herein, are controlled by a programmedcontroller 310. Though this controller is not shown in the otherfigures, it should be assumed that one is present for porposes ofperforming the triggering and establishing the timing of thattriggering.

The following example will illustrate the sequential discharge sequencethat might be implemented by the rectification section in FIG. 19. Ifone charges at the 70° electrical angle, the voltages in three phasesare V₁ /V_(o) =1.88, V₂ /V_(o) =-1.53, and V₃ /V_(o) =-0.35, with theunity being the maximum input voltage. In that case, one would have thefollowing discharge sequence. One starts the sequential dischargesequence in order of decreasing absolute voltage level by firsttriggering SCR1p to discharge C₁. If one chooses to discharge C₁completely, one would trigger SCR2n next at the point in time when C₁ isfully discharged. The bridge circuit permits the flow of current throughthe common inductor Lo that is used in this section, as shown. At thepoint when the voltage of C₂ is zero, one triggers SCR3n to dischargeC₃. The components SCRnn and SCRpn permit the return of current to allthree capacitors. Alternatively, if one uses diodes in place of SCRnnand SCRpn, these components then perform as free wheeling diodes at thepoint where the voltage in C₃ becomes zero. At that point, all theoutput SCRs are off and the recharging of the capacitors of the inputsection (i.e., C1in, C2in, and C3in) can commence for the next dischargecycle.

Alternatively, a second discharge mode may be used that permits a fasterdischarge and also yields a higher output voltage. In this case, SCR1pand SCR2n are triggered simultaneously to discharge C₁ and C₂ together.As capacitor C₂ reaches the zero voltage level, SCR3n is triggered,turning off SCR2n and continuing the discharge of C₁ together with C₃.In a balanced system, both capacitors will reach zero at the same time.Also, the discharge can be stopped at any time by selectively using freewheeling switches at the same time.

We can also trigger the second, third, and free wheeling switches (FWS,e.g. SCRnn and SCRns)) such that residual voltage remains on thecapacitors. For example, if SCR2n is triggered before C₁ reaches zero, apartial residual voltage will be left on the capacitor. If we delay thetriggering, capacitor C₁ will recharge to a negative value. The sameapplies for the last capacitor using the trigger timing of the FWS. Forexample, if one permits a residual voltage with a value of γ as given byEq. 10, one can control the real power without changing the repetitionrate. If one lets γ=0.1 by triggering SCR2n late, capacitor C₁ will becharged up to a negative voltage and power flow is increased, as givenby Eq. 12. The residual voltage requirements for the other two phasesare identical to that of Eq. 10 but shifted in phase by 120° and 240°,respectively.

The above operation permits the use of self-commutating switches orswitches that do not have to be actively opened. Also, since the bridgecircuit does not require an inversion process, this allows one toincrease the throughput. Finally, controlling the residual voltage onthe capacitors permits one to actively control the throughput power witha constant repetition rate. The charging can be directly performed on athree phase AC grid, and a transformer or transformer isolation is notrequired. The residual voltage on the input side also permits us, usingthe inverse or reconstruction process, to synthesize a three phaseoutput voltage higher than the input voltage. This allows us to transferpower from a lower voltage AC bus to higher voltage AC bus. However,this is achieved at the expense of including an additional inversioncycle.

Being able to control real and reactive power flow is of practicalimportance in many applications. In the case of induction generators,for example, both the extraction of real power and the supply of VAR isimportant. To control both real and reactive power flow, the residualvoltage, as given by Eq. 14, must be supplied for each phase. In a latersection, I will give a specific example for a VAR controller.

AC-Reconstruction

As described previously, AC can be reconstructed from a DC bus using asequential charging technique that is the inverse of the sequentialdischarging technique previously described. That is, the threecapacitors are charged in order of increasing output voltagerequirements. For maximum efficiency and minimum number of energytransfer cycles, the preference is to completely discharge the outputcapacitors to obtain maximum charge transfer. However, this is notabsolutely necessary and, in some cases, residual energy may be left inthe capacitors. Indeed, residual energy is required if the output isdesigned for both real and reactive power flow control.

Assuming that the desired reconstructed wave form has a maximum voltageof V_(a) and phase angle ω't, the required charge voltage on each of theoutput capacitors (e.g. capacitors Cout1, Cout2, and Cout3 in FIG. 19 orcapacitors Cm1, Cm2, and Cm3 in FIG. 20) is:

    V.sub.1 =2V.sub.a β.sup.1/2 sin(ω't)            Eq. 27(a)

    V.sub.2 =2V.sub.a β.sup.1/2 sin(ω't-120°)Eq. 27(b)

    V.sub.3 =2V.sub.a β.sup.1/2 sin(ω't-240°)Eq. 27(c)

The energy in each capacitor is thus:

    E.sub.1 =2CβV.sub.a.sup.2 sin.sup.2 (ω't)       Eq. 28(a)

    E.sub.2 =2CβV.sub.a.sup.2 sin.sup.2 (ω't-120°)Eq. 28(b)

    E.sub.3 =2CβV.sub.a.sup.2 sin.sup.2 (ω't-240°)Eq. 28(c)

with the total energy of all three capacitors given by Eq. 28(d) below:

    E.sub.1 =2CβV.sup.2.sub.a (3/2)                       Eq. 28(d)

If β is unity or higher, then the output capacitors will be charged tothe correct voltage for complete energy transfer during the dischargecycle and the product of the energy in the capacitors and the repetitionrate will yield the desired energy flow in each phase and for the totalthroughput. With a lower β the discharge will not be complete and willleave part of the energy in the output capacitors. The sequentialresonant charging process, without the use of opening switches, yields abeta that is proportional to the square of the DC voltage and theinstantaneous phase angle (ω't) of the reconstructed waveform andβ^(1/2) is

    β.sup.1/2 =(2Vdc/3V.sub.a)(| sin(ω't)|+| sin(ω't-120°)|+| sin(ω't-240°)|)

The value of β must be computed for each cycle to permit the correctenergy ratio and the correct power flow in each phase. By properselection of β, we can avoid having to use a turn-off switch and thelast capacitor bank will fully complete its charge transfer cycle andproduce the correct charge voltage. In other words, the energy in theinductor will be completely transferred to the third capacitor and theenergy ratio of all three capacitors will have the correct value foronly one value of β to satisfy Eqs. 27 and 28 without having to eitherprolong or terminate the third capacitor charging process. The β(ω't)value is a function of the required output phase. With a DC or DC businput the inter-pulse duration must be adjusted to compensate for thebeta variation to yield the correct power throughput. From Eqs. 27 and28 it follows that the interpulse duration must be modulated over the360 degree cycle to be inversely proportional to the value of β(ω't).

Plots of β and the interpulse duration are shown in FIGS. 22a and 22b,respectively, for the derectification section of FIG. 19. In bothfigures the horizontal axis is in electrical degrees and in FIG. 22a thevertical axis is in microseconds. The information which is presented inthee two figures is used to control the timing of the SCR triggering. Itcan be computed in real time by the controller or more preferrably itcan be precomputed and stored in a table that is accessible by thecontroller.

The triggering of the SCR can be either controlled by monitoring thevoltage on the capacitor or by precalculating the time the triggeringneeds to be performed with the information of both the input voltage andoutput condition.

The sequential capacitor charging triggering sequence for the DC to ACreconstruction is the inverse of the sequential capacitor dischargingsequence for the rectification process. The circuit which I will use todescribe the derectification process is shown in FIG. 20.

The derectification circuit receives transforms a DC voltage (Vdcin) onits input to a three phase AC output signal. The circuit includes aresonant charging inductor Lin connected through SCSRin1, SCRin2, andSCRin3 to charge storage capacitors Cm1, Cm2, and Cm3, respectively.Each capacitor has a corresponding inverting circuit connected acrossit. The inverting circuits include an SCRvi in series with an inductorLvi, where i=1,2,3. Each of the capacitors is, in turn, connected to oneside of a corresponding output inductor Louti through a pair of SCRs,namely, SCRoin and SCRoip. The SCR's in this pair are connected inparallel and with their polarities in opposite directions. The inputside of each of the inductors Louti is connected to ground (or the otherside of the DC supply) through another pair of SCR's, namely, SCRfwinand SCRfwfwip, which are connected in parallel and with their polaritiesin opposite directions. These pairs of SCR's function as free wheelingSCR's.

Referring to FIG. 20, the SCR for the lowest voltage capacitor istriggered first. As the voltage reaches the desired level, the capacitorrequiring the second highest voltage is then triggered. At that pointthe first SCR is back biased and forced to turn off. The initialcondition for the second capacitor discharge will include the remaininginductor current of the first capacitor charging process. With thevoltage having reached the correct value on the second capacitor, thethird capacitor SCR is then turned on, stopping the charging of thesecond capacitor. The remaining inductor current, forming part of thethird capacitor initial condition, will yield a higher output voltage onthe third and final capacitor. The third capacitor charge cycle iscompleted with all the energy transferred from the inductor to the lastcapacitor. If the β and timing is correctly selected, the energy ratioof all three capacitors will be correct for each cycle. The use of thebridge circuit permits the charging to the correct polarity and allowsthe immediate discharge of the capacitors. The capacitors having theincorrect polarity must to go through an inversion cycle. Thedischarging of the three capacitors can be performed at the same time.Free wheeling SCRs or other switches permit the complete energy outputtransfer or may be used to aid in the control of residual voltage levelsfor output VAR and harmonics compensation.

Using an output bridge circuit such as bridge circuit 306 in FIG. 19permits me to eliminate the inversion process and, as a result, increasethe power throughput. The bridge circuit permits me to charge thecapacitors not only to the correct voltage, but also to the correctpolarity.

Using FIG. 20 and a phase angle of 70 degrees, the three reconstructionvoltages are V₁ =338 V, V₂ =-276 V, and V₃ =-62 V for a 440 V AC output.With a DC supply voltage of Vdcin=393 V DC, we charge the capacitorsCm1, Cm2, and Cm3 in sequence to the 926 V, 756 V and 170 volts,respectively, by triggering SCRin3, SCRin2 and SCRin1 in sequence and atthe correct time. The current through the charging inductor Lin and thevoltage at the output of the charging inductor Lin are shown in FIGS.22a and 22b, respectively.

More specifically, the sequential charging process starts by firsttriggering SCRin3. In response the current through Lin increases andcapacitor Cm3 begins charging to a positive voltage. As soon as thevoltage on Cm3 reaches the correct value, SCRin2 is triggered toterminate the charging of Cm3 and to begin the charging of Cm2. Thecurrent that is in Lin, i.e., Ia) provides an initial condition for thecharging of Cm2 thereby enabling it to charge to a higher value. Duringthe charging of Cm2, the current through Lin increases as shown in FIG.22a. As soon as the voltage across Cm2 reaches the desired value, e.g.756 V, then SCRin1 is triggered to terminate its further charging and tobegin the charging of Cm1. Again the current in inductor Lin when SCRin1is triggered (i.e., Ib) establshes the intitial condition for thecharging of Cm1. As the current through Lin drops to zero, SCRin1 willself-commutate off and the voltage across Cm1 will have its desiredvalue.

Note that the triggering times of SCRin2 and SCRin1 determine thecorrect voltage levels of Cm3 and Cm2, respectively, while Cm1 reachesits correct voltage level as SCRin1 commutates. Since the voltage oncapacitors Cm2 and Cm3 have the incorrect polarity, we trigger SCRv2 andSCRv3 to invert their polarity. With the inversion completed, we triggerthe output SCRs of SCR01p, SCR02n and SCR03n to discharge the capacitorsinto the output filters through the three output inductors. Since β1/2has a value of about 1.37, the capacitors will fully discharge,requiring the triggering of the free wheeling SCRs SCRfw1p, SCRfw2n andSCRfw3n as the capacitor voltage becomes zero to assure full energytransfer. At that point the next recharging cycle may start.

Direct AC to AC Frequency Changer

AC to DC rectification with a DC filter and a derectification sectionpermits AC to AC conversion going through a DC bus, as noted above. Thisarchitecture permits us to connect additional energy storage in parallelwith the filter capacitor to configure it as an uninterruptible powersupply (UPS). However, if there are no energy storage requirements, theDC bus can be eliminated by removing one of the inductors and filters,e.g Cf and Lin of FIG. 19, and by simply connecting the rectificationsection directly to the derectification section (i.e., the ACreconstruction module). This involves combining the sequential dischargecycle of the rectification section with the sequential charge cycle ofthe derectification section. In this case, referring to FIG. 19, theoutput inductor Lo of the discharge cycle is used as the input inductorfor the charge cycle of the output section. The discharging of thecapacitors of the rectification section is simultaneously performed withthe charging of the AC reconstruction section, since they are connectedin series.

The SCR of the capacitor with the highest voltage of the output sectionis triggered first together with the SCR of the lowest voltage capacitorin the input section. As soon as the voltage of the input capacitorreaches the correct value, the SCR for the input capacitor with the nexthighest voltage is triggered. When the output capacitor is discharged orreaches the correct voltage level, the input capacitor with the nexthigher voltage is connected. This process is repeated until all energyhas been transferred. Again, the bridge circuit permits the eliminationof the inversion process for both the rectification and derectificationprocesses. If no bridge circuit is used, an inversion cycle has to beinserted between the simultaneous charge cycle and sequential dischargecycle. The power transfer can be both controlled by the repetition rateand by the control of the residual input capacitor voltage.

The reactive power control may be implemented on both the AC input andAC output end. For most applications, it is best to use only reactivepower control for one end in order to keep the control complexity down.It appears that a good mode of operation is to draw only real power fromthe inputs by controlling the γ parameter of Eq. 9 and then control thereactive power on the output end to supply the reactive demand of theload. This is particularly important if the system is used as a standalone power source, such as a UPS, a variable speed motor drive, or withany other load that has no other AC power source.

As power is transferred from the input capacitors, C1in, C2in, and C3in,through the common inductor Lo, residual voltage and charge may be leftin the input capacitor for the next input charge cycle. This permits oneto draw both real and reactive power from the input source. The voltagerequirement is defined by Eq. 20 for the first phase. The remainingphases are the same, but shifted by -120 and -240 electrical degrees.The operational process for the direct AC to AC frequency changer is thesame as the back to back rectification and derectification system. Themajor exception is that the operation of both processes needs to becoordinated and precisely controlled. This is not a problem usingtoday's controller technology.

The typical operation of an AC to AC frequency changer would be to drawonly real power from the input side and supply both real and reactivepower to the load, such as a variable speed motor. Referring to FIG. 23,such a system could be controlled over its normal operating range byusing no residual voltage and by controlling the power flow with therepetition rate. This mode of operation, which is represented by line400 extending from the origin, yields the best efficiency. However,under maximum power requirements a maximum repetition rate will bereached beyond which the circuitry will not be able to perform. At thatpoint, one can switch into a constant frequency operation and useresidual input voltage control to yield additional power throughput.This mode of operation is represented by the vertical line 402 (alsolabelled Vin≠0) at fmax. It should also be noted that operating with avariable inverter frequency requires a low pass filter. Such a filtersare typically not effective at and below their cut-off frequenciesduring low power operation. Thus, to solve this problem, one can againtransition into a constant frequency operation at lower frequency anduse residual input voltage control to reduce the power throughput in alow power range. This type of operation, which is illustrated by thevertical line 404 (also labelled Vin≠0) located at fmin, could be used,for example, to start a motor, to transition through the low powerrequirement to normal operation, and to provide intermittent high powerrequirement as needed.

Under normal operation, power is typically transferred from one end tothe other with the output voltage being lower than the input voltage.However, with the residual voltage control an output voltage can beprovided that is higher than the input. In addition, since the circuitis symmetrical, the power flow can be controlled in both directions. Itfollows that such a circuit may include regenerative breaking, asrequired for some motor drive applications.

FIG. 19 and the described modifications are only representative of manyother possible circuit configurations. Most of these circuits use thecharge transfer operation between a set of capacitors and an AC system,e.g. a sequential charge transfer operation that typically uses a sharedinductor. With residual voltages in the capacitor, we may control thecharge transfer process to yield the desired, on average, current flowbetween the capacitor and the AC terminal. Depending on the details ofoperational requirements and the system configuration, we may find thatit is desirable to use capacitor polarity inversion circuits.

Reactive Power Control

Static Var Controllers (SVC) operate and are available in both a voltageor a current source mode configuration. The typical voltage source modeconsists of a rectification section transferring power into a voltagesource that consists typically of a charge capacitor bank. It isbasically an inverter operating into a capacitor. The net transfer ofpower between the voltage source and AC system, neglecting losses, iszero. A typical configuration is shown in FIG. 24a. The voltage levelV_(S) typically determines the reactive power flow. The rectificationsection typically consist of power sources shifted in phase with theinput source.

The current source inverter configuration shown in FIG. 24b is a similarscheme with the exception of having circulating current. The currentsource inverter has typically an inductor as the current source. Thetiming in the bridge rectification circuit again determines the energyor VAR flow. The major problem with this configuration is that harmonicsare generated by the inverter. In addition, most available invertersrequire opening switches.

The PCS/SVC, which embodies the invention, can be configured in both thevoltage source and current source inverter mode and it permits directline to line power transfer, eliminating the transformer(s). Since thePCS/SVC inverters can use self-commutation switches, high voltage andhigh power thyristors may be used.

As an example, the PCS AC to DC rectification circuit (previouslydescribed above and in U.S. Ser. No. 08/494,236) can be directlyconfigured as a PCS/SVC voltage source inverter. And, if the capacitoris shorted out, it becomes a modified current source inverter. Theadvantage of the PCS/SVC is its simplicity and, most importantly, itsharmonic-free operation. Furthermore, it essentially yields aninstantaneous response.

Typical PCS/SVC operation

The objective is to inject and extract energy and charge out of eachphase and at a high enough frequency to yield harmonic-free operation.To accomplish this, we set the initial voltages of the capacitors to thecorrect values, as given by Eqs. 14 or 15, for the first phase to obtainthe desired charge transfer between the capacitor bank and the AC systemto meet the average reactive current requirements as given by Eq. 13.The resonant interaction between the working capacitors and the inputline will, according to Eq. 2, yield a final capacitor voltage of:##EQU23## or, stated differently: ##EQU24## where ##EQU25## Comparingthe initial and final capacitor voltages of Eqs. 15 and 30, we see aphase shift of plus and minus β, respectively. Since, according to Eq.17, no net energy has been transferred during the charge transferprocess, the second cycle of the SVC operation is simply to redistributethe capacitor energy to obtain the desired initial capacitor voltage.The voltage is again given by Eq. 15 to be computed at t+Δt, with Δtbeing the time interval between charge interaction.

FIG. 25 shows a circuit configuration for a PSC/SVC. It consists of aninput filtering section 420, an input or charge interchange section 422,and a charge redistribution section 424. The filter section can beeither configured in a γ or Δ configuration and can be either a low passfilter or tuned filters, if operating at a fixed frequency. In the inputfiltering section 420, there is an input filter for each phase of thethree-phase line. Each filter includes an inductor Lfi and a capacitorCfi. The input section 422 includes three charging sections, eachsimilar to the charging sections used in the circuit of FIG. 19 andincluding an inductor Lini, a parallel arrangement of SCR's (i.e., SCRpiand SCRni) with opposite polarities, and a charge storage capacitor Ci.The parallel arrangement of SCR's allows the corresponding capacitor tobe charge from either a positive or a negative voltage source. Thecharge redistribution section includes an inductor Lo connected to thethree capacitors C1, C2, and C3, through a bridge circuit which includesa network of SCR's connected in the manner previously described.

Three input SCRs, one per phase are triggered during a charging period,resulting in a charge transfer as a consequence of the voltages changingin accordance with Eq. 2. In Tables 1 and 2, I have presented thevoltages on capacitors C1-C3 for one such charging sequence occurring ata phase angle of 54 electrical degrees. To simplify, I have normalizedthe voltages and listed them as the ratio of the voltage of thecapacitor to the maximum phase to neutral voltage Vo, as defined inEq. 1. The first column identifies the parameter for which data isprovide in the corresponding row. The second and third columns labeledinitial and final, respectively, contain the "after" and the "before"capacitor voltages for the charge transfer sequence. The initial or"after" voltage is the voltage that exists on the capacitor at the startof the next charge transfer cycle. The 4th row contains a number whichis proportional to the energy in the inductor Lo normalized to the totalenergy stored in the three capacitors. Finally, the bottom columnidentifies--by subscripts--the thyristors which are triggered on foreach operation.

The control and trigger timing of the thyristors permit theredistribution of the energy in the capacitors from the final condition(see column 3) from the last charge transfer sequence to the nextinitial condition (see column 2) for the next capacitor chargingsequence. There are several ways we can accomplish this with the circuitof FIG. 25. Two different illustrative sequences are described for theillustrated phase angle of 54 electrical degree. The first sequencegiven in Table 1 discharges all of the energy in a sequential way intothe output inductor and then recharges the capacitor, using the inductoras a current source to yield the desired initial voltage for the nextcharge transfer with the three phase AC terminal. The dischargingprocess follows the typical PCS rectification procedure described aboveand in U.S. Ser. No. 08/494,236, while the recharging process is similarto the charging process in the derectification process, describedelsewhere in this document. The step by step procedure is presented inTable 1 as steps 1 through 5.

                                      TABLE 1                                     __________________________________________________________________________    Charge Transfer and Distribution Sequence #1                                  Parameter                                                                          Initial                                                                            Final                                                                             step 1                                                                             step 2                                                                            step 3                                                                             step 4                                                                            step 5                                        __________________________________________________________________________    Vc1/Vo                                                                             0.051                                                                              1.567                                                                             0.0  0.0 0.0  0.0 0.051                                         Vc2/Vo                                                                             -1.438                                                                             -0.389                                                                            -0.389                                                                             0.0 0.0  -1.438                                                                            -1.438                                        Vc3/Vo                                                                             1.387                                                                              -1.178                                                                            -1.178                                                                             -1.178                                                                            1.387                                                                              1.387                                                                             1.387                                         E.sub.ind /E.sub.total                                                             0.0  0.0 0.615                                                                              0.652                                                                             0.518                                                                              0.001                                                                             0.0                                           SCRs p1, p2, n3                                                                         all off                                                                           1p, rn                                                                             2n, rp                                                                            3n, rp                                                                             2p, rn                                                                            1n, rp                                        __________________________________________________________________________

The operation of the circuit that is presented in Table 1 is alsoillustrated in FIG. 26 which shows how the capacitor voltages change inresponse to the triggering sequence presented in Table 1. It should benote, however, that for clarity the voltage transitions appearing inFIG. 26 are shown as being linear, when in reality they follow a curvedpaths that are characteristic of resonant charging and dischargingprocesses. I will now explain the steps of the process shown in Table 1.

First, capacitor C1, which has the largest voltage, is discharged bytriggering SCR1p and SCRrn (shown in Table 1 as 1p and rn) (step 1).Capacitor C1 will then begin to transfer its energy to inductor Lo andits voltage will drop towards zero. When the voltage across C1 reacheszero, we then trigger SCR2n and SCRrp which prevents the recharging ofC1 and starts the discharging of C2 (step 2). Note that the triggeringof SCR2n back biases SCR1p, thereby automatically turning off SCR1p(i.e., SCR1p is force-commutated). Capacitor C2 is permitted todischarge to zero voltage at which point SCR3n is turned on, therebyautomatically turning off SCR2n and the flow of current into C2 andallowing C3 to discharge. When the voltage across C3 reaches zero, allof the energy that was originally in the three capacitors, C1, C2, andC3, will now be residing in the inductor Lo. C3 was selected to be thelast discharging capacitor because a voltage polarity change is requiredin C3. In other words, we let C3 transition into a recharging mode andproceed until the voltage on capacitor C3 reaches its required voltage(i.e., 1.387). When the voltage of C3 reaches the correct level, SCR2pand SCRrn are triggered to terminate further recharging of C3 and tobegin the recharging of C2 (step 4). This then completes the secondrecharging step. In step 4, C2 recharges to -1.1438 at which point,SCR1n and SCRrp are triggered to terminate the charging of C2 and beginthe charging of C1 (step 5). At that point, there is only a small amountof energy left in the inductor and, assuming negligible losses, thiswill charge C1 to the final desired voltage. The current in the inductorLo will go to zero and all of the SCRs will self-commutate off. Once thecharge has been completely redistributed in the capacitors, the nextcharge interchange with the grid can take place after which the nextcycle can start.

The advantage of this redistribution scheme is that it is conceptuallysimple. As can be seen from the operation the SCRs, the SCRrp and SCRrncan be replaced by diodes. Its disadvantage is that by discharging allof the capacitors, such as C1 and C2, the losses are potentially higherand more time may be required to complete the charge redistributionprocess. In this regard, note that five steps are required. I will nextdescribe a second sequence that may be more efficient, uses fewer steps,and takes less time.

A second redistribution sequence, which is presented in Table 2 andillustrated in FIG. 27, requires only three steps. In the first step,SCR1p and SCR3n are triggered on at the same time causing both capacitorC1 and C3 to discharge simultaneously (step 1). Notice that in this casethe capacitors with the highest positive and highest negative voltagesare selected to begin the charge redistribution process. As capacitorsC1 and C3 discharge, current builds up in the inductor Lo. The voltageon C1 decreases to zero and C1 then recharges to a negative polarity.Since we cannot turn SCR1p off at its desired voltage of +0.051 volts,we let it continue to discharge and then recharge until it reaches about-1.567 volts. At this point, the voltage on C3 will be 0.916 volts. Wenow trigger SCR2p (step 2). This will back bias SCR1p and stop therecharging of C1 and it cause the charging of C2 and C3. As the voltageon C3 reaches its desired voltage of 1.387, we trigger SCR1n to turn offthe charging of C3 and to begin charging C1 to a positive voltage (step3). At this time, both C1 and C2 are charging. We let this chargingprocess go to completion and obtain a final voltage of 0.051 volts on C1and -1.438 volts on C2. At that point, all of the energy from theinductor Lo has been dumped back into the capacitors, the currentthrough Lo begins to reverse and all of the SCRs self-commutate to off,thereby permitting the next charge interchange with the AC grid.

                  TABLE 2                                                         ______________________________________                                        Charge transfer and Distribution Sequence #2                                  Parameter                                                                            Initial   Final   step 1  step 2                                                                              step 3                                 ______________________________________                                        Vc1/Vo 0.051     1.567   -0.528  -0.528                                                                              0.051                                  Vc2/Vo -1.438    -0.389  -0.389  -0.859                                                                              -1.438                                 Vc3/Vo 1.387     -1.178  0.916   1.387 1.387                                  E.sub.ind /E.sub.total                                                               0.0       0.0     0.662   0.263 0.0                                    SCRs   p1, p2, n3                                                                              all off 1p, 3n  2p, 3n                                                                              2p, 1n                                 ______________________________________                                    

The second sequence (Table 2) is faster and more efficient than thefirst sequence (Table 1). First, the charge flows only through half asmany solid state devices. Second, the energy in the capacitors is notcompletely discharged, as can be seen in the 4^(th) row. Third, thenumber of steps is reduced from 5 to 3. In addition, the distributionbridge circuit can be reduced to a total number of six SCRs byeliminating SCRrp and SCRrn, which are not needed.

The triggering sequences given in the 5th row remain the same over aphase angle of 60 degrees, and only the timing needs to be changed. Foreach subsequent sixty degree phase angle, the SCR designations have tobe permutated. Also, the three step operation can be utilized over thecomplete AC cycle.

It should be understood that the above-described triggering sequencesare by no means the only workable sequences. Other triggering sequences,which can be readily determined by persons skilled in the art, exist andcan also be used. In any case, the main objective is to redistribute thecharge in the capacitors so that the next charge transfer with the ACsystem can take place. Moreover, it may be desirable that the sequenceof triggering be selected so that the switches self-commutate off. Ifself-commutation is not necessary or desired (for example, if switchessuch as GTO's are used which can be turned off), then other triggeringsequences can be used.

Active Harmonics Filter

For a balanced system, a PSC/SVC does not need to store and injectenergy, since the combined power flow of all three phases is zero. Thisalso applies for the harmonics power flow for the 3rd, 6th, 9th, etc.harmonics. It follows that one can combine the VAR and harmoniccorrection for harmonics that are a multiple of three, and the circuitand the triggering sequences described in the previous section, can beused.

For the remaining harmonics, however, power must be stored andre-injected into the AC system during a complete AC cycle. This requiresenergy storage that must be sufficient to satisfy the total energyfluctuations which will occur. Obviously, both a voltage source inverterand a current source inverter may be used for harmonics mitigation. In avoltage source inverter, the size of the capacitor must be selected tomeet the power fluctuations. To store energy in a current sourceinverter, the energy has to be stored in the inductor with currentflowing all the time.

A third approach is to modify the PCS/SVC current source inverter topermit its operation in the current source mode while also addingcapacitor energy storage. Such a circuit is shown in FIG. 28 and itsoperation is described below. This circuit is identical to the circuitof FIG. 25 except for the addition of Ces to store energy that can beinjectd back into or extract from the capacitors C1, C2, and C3 throughtwo SCR's, i.e., SCRsp and SCRsn. This is only one of several circuitconfigurations that can be used. The basic process involves a firstcycle during which charge is interchanged between the grid and a set ofcharged capacitors, and a second cycle during which the energy in thecharged capacitors is redistributed. During the redistribution cycle,energy is either absorbed or supplied, depending on what the capacitorvoltage distribution requires. The charge storage in the capacitorsappears to yield good efficiency and can be implemented usingcommercially available components.

With the harmonics give by: ##EQU26## the initial capacitor voltagerequirement is: ##EQU27## This results in a final capacitor voltage of:##EQU28##

Following a charge interchange, the energy in the capacitor is given byEq. 34. The new initial voltage requirement for the next interchange isgiven by Eq. 33. Since this interchange occurs at t+Δt, where Δt is theinterval between charge interchanges, the initial voltage has to becomputed for the next interchange. Performing the same computation forthe other two phases, by replacing ωt with ωt-π2/3 and ωt-π5/3,respectively, produces the complete set of initial voltages for the nextcharge transfer condition. With this information, we can determine thenet increase and or decrease of the energy for this specificinterchange. If a net energy absorption is required, energy will bedeposited in the energy storage capacitor Ces or if a net energyincrease is required, energy will be released from the energy storagecapacitor Ces.

The energy redistribution in the three capacitors is similar to thePSC/SVC operation described above. Conceptually, the simplestredistribution sequence would follow the process in Table 1 where all ofthe capacitors are being discharged into the inductor Lo during thefirst half of the distribution cycle. With the three normalized voltagesbeing 1.567, -0.389, and -1.178 and with the energy storage capacitorvoltage Ves/Vo being 1.00, we may proceed to the step 1 sequence byfirst extracting the necessary energy from Ces by triggering SCRsp andSCRrn. As soon as the additional energy for the next charge transfer hasbeen extracted, we trigger SCR1p to terminate the energy extraction fromCes, shut off SCRsp, and proceed with the complete extraction of thethree charge exchange capacitor. The only requirement is that thecapacitor discharged after the energy extraction from Cep has anabsolute voltage higher than the Ces voltage. The recharging of thecapacitor can proceed in the same order and if the extracted energy andthe computation was correct the desired voltage level will be obtained.

On the other hand, if energy needs to be absorbed from the set of threecapacitors, we insert a charge sequence by triggering SCRsp. For theconditions shown in Table 1, such a sequence may, for example, beinserted between step 3 and step 4 or between step 4 and step 5, if thenormalized voltage of Ces is on the order of 1.0.

Similar analysis indicates that either extraction or deposition cyclescan be inserted into the second sequence described in Table 2. Theimportance is that the capacitor size and voltage requirements must besuch that the Ces voltage is in the average capacitor range. With thecapacitor voltage identified, the capacitor value must reflect themagnitude of the total harmonics correction requirement. This circuitcan operate with either positive or negative voltage polarity.

The utilization and integration of an energy storage circuit, asdescribed above, is not limited to the harmonics mitigation operationbut can be also used for several other functions. This includes thesimplified AC to AC frequency changer covered in the next section, UPSand SVC. In the SVC, VAR level changes requiring a change of energy inthe working capacitors, as given by Eq. 17, may be implemented moreeffectively.

Simplified AC--AC Converter

For the SVC application shown in FIG. 25, the three capacitor voltagesand energy are redistributed for the next charge interaction with theinput grid. The redistribution does not produce any energy change and,during the redistribution phase, the voltages in all three capacitorsare shifted in phase by a specific number of electrical degrees. Thechange in the electrical angle is the difference between the phase angleof the initial voltage and the final voltage. For the SVC, the phaseangle change is two times the expression given by Eq. 31. However, withthe redistribution technique described above, we may change the phaseangle from any phase angle to any other phase angle with a phase angledifference from zero to 360 electrical degrees. This permits us toconfigure a frequency changer as shown in the simplified schematic asshown in FIG. 29. This circuit is the same as the circuit shown in FIG.25 but with the addition of a derectification section added at itsoutput to inject power onto a second grid. In other words, rather thansimply feeding the energy back onto the original grid, as was the casefor the circuit of FIG. 25, we inject it onto another grid and at thefrequency used on that grid (which may be different from the frequencyused on the first grid).

After charging the three capacitors from the input grid, starting witheither residual voltage or no residual voltage on the capacitors, weredistribute the energy in these capacitors to obtain a voltage to matchthe phase of the desired three phase output. With the redistributioncomplete, the additional SCR's SCRjoi can be used to discharge thecapacitor energy into the output. This permits the reconstruction of amultiphase AC output with any frequency and any phase. In addition tothe output filter shown, we may add free-wheeling SCR's to add fullpower transfer control or further residual energy control.

The circuit shown may be used to transfer real power from one end to theother end. This requires a charge cycle from the input, a redistributionof the energy stored in the three capacitors to yield both the correctenergy and voltage polarity, and a discharge cycle to the designatedoutput. Both real and reactive power can be controlled on either end byadding an additional redistribution cycle between the discharge cycleand the next charge cycle. The energy for this redistribution cycle mayoriginate from an incomplete discharge or by drawing reactive power fromthe output. The redistribution of the energy can be performed to aid thecontrol of both real and reactive power demand of either the input oroutput or both.

Since the circuit can be configured to be symmetrical, it should beobvious that the power flow can be bidirectional. Using residualvoltage, power flow can be also provided and controlled originating froman input power source having a voltage that is lower than the outputvoltage. The basis of this requirement is given above.

In addition to the real power transfer and VAR control, we may implementharmonic cancellation and harmonic current injection as has beendescribed in previous section. Both the charge and discharge consists ofa charge transfer between a set of capacitors and a multiphase ACterminal. This interchange may be configured to operate in any mode ofoperation, as described above. In addition, it should also be obviousthat the charge interchange is not restricted to two AC terminalssystem. For example, an additional input would permit the power transferbetween three terminals, with a two bus input and one bus output aninstantaneous input bus transfer may be implemented should a problemwith the power supply of one bus occur. In addition, power can be drawnin any power ratio from the two inputs or power transfer may beperformed over any selected time.

Further Techniques for Real and Reactive Power Flow Control

If the PCS system transfers power from either an AC or DC source andinjects that power into an existing AC network it is desirable totransfer only real power to that system. It follows that the system intowhich the power is injected will handle the reactive power of the load.However, if we reconstruct an AC waveform and no other means isavailable to source the reactive power by the line or the load, then thesystem must supply both the real and the reactive power.

FIG. 30 shows a block diagram of a basic PCS flow control configurationwith real power P drawn from the left. The configuration includes a PCSmodule 500, a multi-phase power line 502, a load 504, and a shuntcontroller 506. Power (P) may be AC or DC and may go through a voltagetransformation process provided by the PCS module 500. The powerprovided by the PCS module 500 and the shunt controller 506 has tosupply both the real and reactive power for the load 504. This can beexpressed mathematically in the following form:

    P.sub.PCS +P.sub.SC =P+Q                                   Eq. 35

where

    P=3.sup.1/2 I.sub.L V.sub.L cos(θ)                   Eq. 36

    Q=3.sup.1/2 I.sub.L V.sub.L sin(θ)                   Eq. 37

    P.sub.φ (t)=VφI.sub.o sin.sup.2 (ωt)         Eq. 38

    Q.sub.φ (t)=VφI.sub.r cos(ωt) sin (ωt) Eq. 39(a)

     =VφI.sub.r sin(2ωt)/2                           Eq. 39(b)

Eqs. 38 and 39 give the time dependent terms of the real and reactivepower of one phase, where Vφ is the maximum phase to neutral voltage,and I_(o) and I_(r) are the maximum real and reactive currents,respectively. As an example, real power, reactive power and total powerare plotted in FIG. 31. The important point is that the real power termis only positive, indicating that real power is flowing only to theload; while the reactive power flow oscillates back and forth to theload at twice the line frequency (2ωt).

In principle, both mathematically and also from a circuit and componentpoint of view, the PCS module can be configured to supply both real andreactive power. This, of course, completely eliminates the need for aShunt Controller. However, this is not too practical for both high powerapplications that require voltage transformation. The reverse powerrequires additional PCS cycles, thus reducing the power throughput. Inaddition, the losses are significantly increased.

Full Static VAR Operation

Another option is to configure the shunt controller 506 as a static VARcompensator (SVC), as described above. It follows that the power P thatis supplied by the PCS module 500 and the shunt controller 506 do nothave to be coordinated and the devices can be separated. However, it ispractical to have them share the same output filter and to synchronizeboth units to minimize filter requirements. Synchronization is easilyaccomplished by using the same controller to control both modules. Thecoordination and control is desirable if no real power is drawn from thefilter and the capacitive elements draw reactive power, allowing thevoltage and the frequency to be maintained. In this case, the shuntcontroller 506, in its SVC mode, supplies the reactive power and itsupplies the timing required to maintain the specified frequency. ThePCS module 500, on the other hand, monitors the real load requirementsand maintains the output voltage at the specified output voltage. Underthis condition, the shunt controller 506 supplies the reactive power andmaintains the oscillatory waveform, by recirculating the reactive powerbetween the three phases at the desired frequency.

Negative Power Shunt Control Operation

FIG. 32 shows the total power flow of one phase to the output load withthe reactive power being of the order of the real power. The totalpower, as shown per phase, is positive if the sum of the reactive andreal power to the load is positive. This implies that power is flowingto the load and that all of that power can be delivered by the PCSmodule. On the other hand, if the sum is negative, the power flow isfrom the inductive part of the load back to the source. In thisoperating mode, either the PCS module or the shunt controller has toabsorbed that returning power in order to maintain a sinusoidalwaveform.

As shown, only a small fraction of net power has to circulate back tothe power source. It is significantly less than the reactive powerrecirculated by the SVC above. In the interest of efficiency, the shuntcontroller 506 can be operated to only absorb the negative powerreturning from the load (shown below the base line in FIG. 32). Thepower absorbed by the shunt controller 506 from the phase shown is beingre-injected into one or both of the other two phases. To yield the totalpositive power flow for each phase, as shown above the baseline, the PCSmodule output provides the rest of the positive power flow. Theoperation of both the shunt controller and the PCS module arecoordinated and synchronized.

The synchronization reduces the current flow requirements through theshunt controller and with it, reduces the losses. On the other hand,positive power flows through the PCS Module at maximum efficiency.

If the shunt controller is used as an SVC, it can also be used as anegative power controller. In addition, an SVC can also performharmonics correction in both the SVC mode and the Negative Power flowControl (NPC) mode. If only shunt control is required, however, with thereal and reactive load being of equal magnitude, the shunt controllercan be simplified and reduced in cost by reducing the component count,since only the energy that is absorbed from one phase will bere-injected into another phase. FIG. 33 shows such a simplified shuntcontroller. In this configuration it is assumed that an output filter518 is shared by both PCS module and the shunt controller. The shuntcontroller includes a bridge circuit 520, similar to those describedbefore, and it includes a shunt capacitor Csh in series with an inductorLsh. An inverting SCR SCRinv is connected in parallel with the seriesconnected Csh and Lsh.

The bridge circuit 520 permits the extraction of the negative flowingpower out of the filter, with the line voltage at either a positive or anegative potential. The energy deposited in the capacitor Csh from oneof the lines is then re-injected into one of the two other linesfollowing an inversion using SCRinv. A multiple charge cycle may beadopted to build up the voltage in Csh to eliminate re-injection voltageissues. However, this should not be a problem for most applications.What is of importance is that the charge, discharge, and inversioncycles use Lsh. Each cycle may yield a complete half cycle waveform.This operation is compatible with high voltage thyristors and theirhigher tq and does not require inverter grade thyristors.

This type of shunt controller is only applicable if the period of thenegative power is 60 electrical degree or less. This is not a full SVCand is to be used in conjunction with a PCS module. The PCS module couldbe a derectification module or AC to AC module with or withouttransformation. Its cost simplicity and high overall electricalefficiency will make it both technically and economically attractive.

Direct reactive power control of a Derectification Module

As described above, FIG. 20 illustrates the basic circuit of aderectification module. Two such modules can be run in parallel for a144 kVA variable speed motor drive application. For operation at lowoutput frequency, the voltage waveform will be satisfactory without theneed for full static VAR support. However, at 80 Hz operation, voltagedistortion are more likely to occur which may or may not influence theperformance of the motor.

In applications where no voltage transformation is performed, the basicderectification circuit can be used to fully support the VAR or negativepower follow provided the negative power flow does not extend over morethan 60 electrical degrees. I will discuss this mode of operation usingthe circuit of FIG. 20.

FIG. 32, shows the real, reactive and total power requirement for areactive load of phase 1. The real power requirements can be met bysequentially charging the capacitors to the correct voltage ratio fromthe DC input source. We will focus on the negative power flowrequirement of phase 1 over the range of 134 to 180 and 314 to 360electrical degrees. Over the first range, the voltage is positive andbecomes zero at the 180 degree point. To draw power from the filtercapacitor, SCRo1n is triggered to back-charge Cm1 to a positive value,as shown in the plot of FIG. 34. If the residual voltage was zero (note:this is not absolutely necessary), the capacitor voltage will be twicethat of the output filter voltage. Next SCRv1 is triggered to invert thepolarity of Cm1. This yields a negative capacitor voltage. We nextperform the sequential charging process of all three capacitors by firsttriggering SCRin1. This discharges the Cm1 capacitor until the voltageis zero followed by a recharge to a positive polarity. SCRin1 is turnedoff by triggering either SCRin2 or SCRin3 and Cm1 having a slightlypositive potential. Capacitor Cm1 is almost completely discharged andthe charging of the Cm2 and Cm3 proceeds to the desired voltage level.The energy of Cm1 was momentarily transferred to the Lin inductor andthen distributed to Cm2 and Cm3 capacitors. The initial current causedby the Cm1 energy discharge will cause a net energy input to the othertwo capacitors. The desired output power can be obtained by adjustingthe interpulse duration and the energy ratio between Cm2 and Cm3. Also,energy transfer flexibility can be obtained by controlling the remainingCm1 voltage, through the discharge timing.

The operation requires three cycles, with one being synchronized withthe charging of the other two phases. Since the other two phases requirealso three cycles, the reverse power flow does not increase the totaltime of the derectification process. Going through a similar processover the 314 to 360 degree range yields similar results. However, sincethe voltage on capacitor Cm1 is negative the inversion cycle is notneeded reducing it to a total of two cycles.

In summary, the real and reactive power can be supplied to a load usingthe circuit of FIG. 20 provided that the extent of the negative powerflow is less than 60 degrees. Since most AC loads fall into thiscategory, this approach can be used without an increase of additionalhardware. Adding the control for the negative power section will onlyrequire the modification of the derectification control algorithm.

It should be understood that the charge transfer cycles described hereintypically occur at a frequency that is higher than 60 Hz, e.g 1 kHz andabove. In other words, the frquency f that was referred to above isgreater than 60 Hz and usually greater than about 1 kHz.

Other embodiments are within the following claims. For example, thoughthe sequential discharge technique has been described in the context ofrectification, it can also be used to reconstruct AC waveforms of anyfrequency and/or phase. The triggering sequence that is generated by thecontrol module would, of course, have to be different and would likelybe more complicated; however, the principles are the same.

The desired rate of the charging and discharging dictate the values ofthe L and C components that are used in the circuit. In the describedembodiment, the inductors on the input side and the inductors on theoutput side have been described as having the same value. This, however,need not be the case.

I claim:
 1. A system for controlling VAR of a multiphase grid, saidsystem comprising:a plurality of charge storage elements; a plurality ofcharge transfer circuits each connected to a corresponding phase of themultiphase grid and to a corresponding one of the plurality of chargestorage elements; and a charge redistribution circuit connected to theplurality of charge storage elements, wherein during operation thecharge redistribution circuit redistributes charge among the pluralityof charge storage elements.
 2. The system of claim 1 further comprisinga controller which operates the plurality of charge transfer circuitsand the charge redistribution circuit, wherein during operation thecontroller causes the plurality of charge transfer circuits to transfercharge to the plurality of charge storage elements, causes the chargeredistribution circuit to redistribute the charge that was transferredto the plurality of charge storage elements, and causes the chargetransfer circuit to transfer the redistributed charge to the grid.
 3. Apower flow control system for connecting to a multiphase grid, saidsystem comprising:a plurality of charge storage elements; a plurality ofcharge transfer circuits each connected to a corresponding phase of themultiphase grid and to a corresponding one of the plurality of chargestorage elements; a charge redistribution circuit connected to theplurality of charge storage elements, wherein during operation thecharge redistribution circuit redistributes charge among the pluralityof charge storage elements; and a controller which operates theplurality of charge transfer circuits and the charge redistributioncircuit, wherein said controller controls the power flow into the systemby establishing non-zero current initial conditions on the plurality ofcharge storage elements prior to a charge transfer cycle during whichcharge is exchanged between the grid and the charge storage elements. 4.A derectification system for generating from a power source a multiphaseAC output onto a grid, said system comprising:a plurality of chargetransfer elements; a first charge transfer circuit which charges theplurality of charge storage elements from the power source; a secondcharge transfer which transfer charge between the plurality of storageelements and the multiphase grid; and a controller which operates thefirst and second charge transfer circuits, wherein the controller causesthe first transfer circuit to sequentially charge the plurality ofcharge storage elements to respective different voltages and in order ofincreasing voltage, starting with the charge storage element with thelowest voltage and ending with the charge storage element with thehighest voltage.
 5. In a system including a plurality of charge storageelements that are coupled to a power source through a circuit whichincludes an inductor, a method of generating a multiphase AC output ontoa grid, said method comprising:sequentially transferring charge betweenthe power source and each of the plurality of charge storage elements sothat each of said charge storage elements is characterized by a voltagecorresponding to the charge stored therein; and transferring chargebetween each of said plurality of charge storage elements and acorresponding one of said phases on said grid, wherein the process ofsequentially transferring charge is performed in order of increasingvoltage of the charge storage elements.
 6. In a system which includes aplurality of charge storage elements, a method of controlling power flowbetween a multiphase grid and said system, said methodcomprising:establishing non-zero current initial conditions in theplurality of charge storage elements; and after establishing non-zerocurrent initial conditions in the plurality of charge storage elements,transferring charge between the multiphase grid and the plurality ofcharge storage elements.